979 resultados para Electrochemistry, Titanium Compounds, Nanotubes, Association, Calcination, Current Density, Electrochemical Electrodes


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Résumé : L’interaction entre la douleur et le système moteur est bien connue en clinique et en réadaptation. Il est sans surprise que la douleur est un phénomène considérablement invalidant, affectant la qualité de vie de ceux et celles qui en souffrent. Toutefois, les bases neurophysiologiques qui sous-tendent cette interaction demeurent, encore aujourd’hui, mal comprises. Le but de la présente étude était de mieux comprendre les mécanismes corticaux impliqués dans l’interaction entre la douleur et le système moteur. Pour ce faire, une douleur expérimentale a été induite à l’aide d’une crème à base de capsaïcine au niveau de l’avant-bras gauche des participants. L'effet de la douleur sur la force des projections corticospinales ainsi que sur l’activité cérébrale a été mesuré à l’aide de la stimulation magnétique transcrânienne (TMS) et de l’électroencéphalographie (EEG), respectivement. L’analyse des données EEG a permis de révéler qu'en présence de douleur aiguë, il y a une augmentation de l’activité cérébrale au niveau du cuneus central (fréquence têta), du cortex dorsolatéral préfrontal gauche (fréquence alpha) ainsi que du cuneus gauche et de l'insula droite (toutes deux fréquence bêta), lorsque comparée à la condition initiale (sans douleur). Également, les analyses démontrent une augmentation de l'activité du cortex moteur primaire droit en présence de douleur, mais seulement chez les participants qui présentaient simultanément une diminution de leur force de projections corticales (mesurée avec la TMS t=4,45, p<0,05). Ces participants ont également montré une plus grande connectivité entre M1 et le cuneus que les participants dont la douleur n’a pas affecté la force des projections corticospinales (t=3,58, p<0,05). Ces résultats suggèrent qu’une douleur expérimentale induit, chez certains individus, une altération au niveau des forces de projections corticomotrices. Les connexions entre M1 et le cuneus seraient possiblement impliquées dans la survenue de ces changements corticomoteurs.

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Dissertação (mestrado)—Universidade de Brasília, Instituto de Química, Programa de Pós-Graduação em Química, 2015.

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Dissertação (mestrado)—Universidade de Brasília, Instituto de Química, Programa de Pós-Graduação em Química, 2015.

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The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.