Detection of SFBC-OFDM signals in frequency- and time-selective MIMO channels

Use of space-frequency block coded (SFBC) OFDM signals is advantageous in high-mobility broadband wireless access, where the channel is highly time- as well as frequency-selective because of which the receiver experiences both inter-symbol interference (ISI) as well as inter-carrier interference (10). ISI occurs due to the violation of the 'quasi-static' fading assumption caused due to frequency- and/or time-selectivity of the channel. In addition, ICI occurs due to time-selectivity of the channel which results in loss of orthogonality among the subcarriers. In this paper, we are concerned with the detection of SFBC-OFDM signals on time- and frequency-selective MIMO channels. Specifically, we propose and evaluate the performance of an interference cancelling receiver for SFBC-OFDM which alleviates the effects of ISI and ICI in highly time- and frequency-selective channels.

Detection of multicode STBC signals in frequency selective fading

Multicode operation in space-time block coded (STBC) multiple input multiple output (MIMO) systems can provide additional degrees of freedom in code domain to achieve high data rates. In such multicode STBC systems, the receiver experiences code domain interference (CDI) in frequency selective fading. In this paper, we propose a linear parallel interference cancellation (LPIC) approach to cancel the CDI in multicode STBC in frequency selective fading. The proposed detector first performs LPIC followed by STBC decoding. We evaluate the bit error performance of the detector and show that it effectively cancels the CDI and achieves improved error performance. Our results further illustrate how the combined effect of interference cancellation, transmit diversity, and RAKE diversity affect the bit error performance of the system.

False Error Study of On-line Soft Error Detection Mechanisms

With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double sampling checker (used in Razor), is the simplest and most area and power efficient, but suffers from very high false detection rates of 1.15 times the actual error rates. We also find that the alternate approaches of triple sampling and integrate and sample method (I&S) can be designed to have zero false detection rates, but at an increased area, power and implementation complexity. The triple sampling method has about 1.74 times the area and twice the power as compared to the Double Sampling method and also needs a complex clock generation scheme. The I&S method needs about 16% more power with 0.58 times the area as double sampling, but comes with more stringent implementation constraints as it requires detection of small voltage swings.