Assessing an FPGA implemented MIMO testbed with the use of channel emulator

In this paper, a channel emulator for assessing the performance of MIMO testbed implemented in a field programmable gate array technology is described. The FPGA based MIMO system includes a signal generator, modulation/demodulation and space time coding/decoding modules. The emulator uses information about a wireless channel from computer simulations or actual measurements. In simulations, a single bounce scattering model for an indoor environment is applied. The generated data is stored in the FPGA board. The tests are performed for a 2times2 MIMO system that uses Alamouti scheme for space coding/decoding. The performed tests show proper operation of the FPGA implemented MIMO testbed. Good agreement between the results using measured and simulated channel data is obtained.

Investigations into the effect of LOS signal blocking on capacity of an indoor MIMO system

In indoor environments the properties of communication channel are affected by the presence of various objects which block the Line Of Sight signal propagation. For example, this occurs because of presence of movement of humans and furniture. In this paper, the effect of reflection and scattering due to the presence of such objects is studied with respect to the capacity of a multiple input multiple output (MIMO) wireless system. The carried out investigations are performed by applying a simple electromagnetic model, in which transmitting and receiving antennas of MIMO system, as well as signal blocking objects, are represented by wire dipoles. In order to provide a fair assessment, calculations of MIMO capacity are performed under both fixed transmitted power and fixed received power conditions.

Design of MIMO testbed with an FPGA board for fast signal processing

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

Design of complementary UWB printed monopole antennas using simple formulas

Simple design formulas for designing ultra wideband (UWB) antennas in the form of complementary planar monopoles are described and their validity is tested using full electromagnetic wave simulations and measurements. Assuming dielectric substrate with relative permittivity of 10.2, the designed antennas feature a small size of 13 mmtimes26 mm. They exhibit a 10 dB return loss bandwidth from 3 to more than 15 GHz accompanied by near omnidirectional characteristics and good radiation efficiency throughout this band