Non-ohmic contact resistance and field-effect mobility in nanocrystalline silicon thin film transistors

Contact resistance has a significant impact on the electrical characteristics of thin film transistors. It limits their maximum on-current and affects their subsequent behavior with bias. This distorts the extracted device parameters, in particular, the field-effect mobility. This letter presents a method capable of accounting for both the non-ohmic (nonlinear) and ohmic (linear) contact resistance effects solely based upon terminal I-V measurements. Applying our analysis to a nanocrystalline silicon thin film transistor, we demonstrate that contact resistance effects can lead to a twofold underestimation of the field-effect mobility. © 2008 American Institute of Physics.

Precursor flow rate manipulation for the controlled fabrication of twin-free GaAs nanowires on silicon substrates

Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metal-organic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH 3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance. © 2012 IOP Publishing Ltd.

Taper-free and kinked germanium nanowires grown on silicon via purging and the two-temperature process

We investigate the growth procedures for achieving taper-free and kinked germanium nanowires epitaxially grown on silicon substrates by chemical vapor deposition. Singly and multiply kinked germanium nanowires consisting of 111 segments were formed by employing a reactant gas purging process. Unlike non-epitaxial kinked nanowires, a two-temperature process is necessary to maintain the taper-free nature of segments in our kinked germanium nanowires on silicon. As an application, nanobridges formed between (111) side walls of V-grooved (100) silicon substrates have been demonstrated. © 2012 IOP Publishing Ltd.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

A discretized proportional base driver for Silicon Carbide Bipolar Junction Transistors

Silicon Carbide Bipolar Junction Transistors require a continuous base current in the on-state. This base current is usually made constant and is corresponding to the maximum collector current and maximum junction temperature that is foreseen in a certain application. In this paper, a discretized proportional base driver is proposed which will reduce, for the right application, the steady-state power consumption of the base driver. The operation of the proposed base driver has been verified experimentally, driving a 1200V/40A SiC BJT in a DC-DC boost converter. In order to determine the potential reduction of the power consumption of the base driver, a case with a dc-dc converter in an ideal electric vehicle driving the new European drive cycle has been investigated. It is found that the steady-state power consumption of the base driver can be reduced by approximately 63 %. The total reduction of the driver consumption is 2816 J during the drive cycle, which is slightly more than the total on-state losses for the SiC BJTs used in the converter. © 2013 IEEE.

All-chemical vapor deposited graphene/silicon nitride TFTs

All-chemical vapor deposited silicon nitride / monolayer graphene TFTs have been fabricated. Polychromatic Raman spectroscopy shows high quality monolayer graphene channels with uniform coverage and significant interfacial doping at the source-drain contacts. Nominal mobilities of approximately 1900 cm 2V-1s-1 have been measured opening up a potentially useful platform for analogue and RFR-based applications fabricated through allchemical vapor deposition processes. © The Electrochemical Society.

Silicon on insulator thermodiode with extremely wide working temperature range

This paper presents for the first time the performance of a silicon-on-insulator (SOI) p-n thermodiode, which can operate in an extremely wide temperature range of 200°C to 700°C while maintaining its linearity. The thermodiode is embedded in a thin dielectric membrane underneath a tungsten microheater, which allows the diode characterization at very high temperature (> 800°C). The effect of the junction area (Aj) on the thermodiode linearity, sensitivity and self-heating is experimentally and theoretically investigated. Results on the long-term diode stability at high temperature are also reported. © 2013 IEEE.

High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/μ), very high resolution (4 n), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes. © 2013 IEEE.

Model for quantum efficiency of guided mode plasmonic enhanced silicon Schottky detectors

Plasmonic enhanced Schottky detectors operating on the basis of the internal photoemission process are becoming an attractive choice for detecting photons with sub bandgap energy. Yet, the quantum efficiency of these detectors appears to be low compare to the more conventional detectors which are based on interband transitions in a semiconductor. Hereby we provide a theoretical model to predict the quantum efficiency of guided mode internal photoemission photodetector with focus on the platform of silicon plasmonics. The model is supported by numerical simulations and comparison to experimental results. Finally, we discuss approaches for further enhancement of the quantum efficiency.

Optimization of efficiency-loss figure of merit in carrier-depletion silicon Mach-Zehnder optical modulator.

In this paper we study the optimization of interleaved Mach-Zehnder silicon carrier depletion electro-optic modulator. Following the simulation results we demonstrate a phase shifter with the lowest figure of merit (modulation efficiency multiplied by the loss per unit length) 6.7 V-dB. This result was achieved by reducing the junction width to 200 nm along the phase-shifter and optimizing the doping levels of the PN junction for operation in nearly fully depleted mode. The demonstrated low FOM is the result of both low V(π)L of ~0.78 Vcm (at reverse bias of 1V), and low free carrier loss (~6.6 dB/cm for zero bias). Our simulation results indicate that additional improvement in performance may be achieved by further reducing the junction width followed by increasing the doping levels.

Waveguide based compact silicon Schottky photodetector with enhanced responsivity in the telecom spectral band.

We experimentally demonstrate an on-chip compact and simple to fabricate silicon Schottky photodetector for telecom wavelengths operating on the basis of internal photoemission process. The device is realized using CMOS compatible approach of local-oxidation of silicon, which enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. The photodetector demonstrates enhanced internal responsivity of 12.5mA/W for operation wavelength of 1.55µm corresponding to an internal quantum efficiency of 1%, about two orders of magnitude higher than our previously demonstrated results [22]. We attribute this improved detection efficiency to the presence of surface roughness at the boundary between the materials forming the Schottky contact. The combination of enhanced quantum efficiency together with a simple fabrication process provides a promising platform for the realization of all silicon photodetectors and their integration with other nanophotonic and nanoplasmonic structures towards the construction of monolithic silicon opto-electronic circuitry on-chip.