Modeling Architecture-OS interactions using Layered Queuing Network Models

The prevalent virtualization technologies provide QoS support within the software layers of the virtual machine monitor(VMM) or the operating system of the virtual machine(VM). The QoS features are mostly provided as extensions to the existing software used for accessing the I/O device because of which the applications sharing the I/O device experience loss of performance due to crosstalk effects or usable bandwidth. In this paper we examine the NIC sharing effects across VMs on a Xen virtualized server and present an alternate paradigm that improves the shared bandwidth and reduces the crosstalk effect on the VMs. We implement the proposed hardwaresoftware changes in a layered queuing network (LQN) model and use simulation techniques to evaluate the architecture. We find that simple changes in the device architecture and associated system software lead to application throughput improvement of up to 60%. The architecture also enables finer QoS controls at device level and increases the scalability of device sharing across multiple virtual machines. We find that the performance improvement derived using LQN model is comparable to that reported by similar but real implementations.

FREP: A Soft-Error Resilient Pipelined RISC Architecture

Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

Continous Time Sigma-Delta Modulator Employing a Novel Comparator Architecture

A novel comparator architecture is proposed for speed operation in low voltage environment. Performance comparison with a conventional regenerative comparator shows a speed-up of 41%. The proposed comparator is embedded in a continuous time sigma-delta ADC so as to reduce the quantizer delay and hence minimizes the excess loop delay problem. A performance enhancement of 1dB in the dynamic range of the ADC is achieved with this new comparator. We have implemented this ADC in a standard single-poly 8-Metal 0.13 mum UMC process. The entire system operates at 1.2 V supply providing a dynamic range of 32 dB consuming 720 muW of power and occupies an area of 0.1 mm2.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.

Fault-tolerant Video on Demand in RSerPool Architecture

With the advent of Internet, video over IP is gaining popularity. In such an environment, scalability and fault tolerance will be the key issues. Existing video on demand (VoD) service systems are usually neither scalable nor tolerant to server faults and hence fail to comply to multi-user, failure-prone networks such as the Internet. Current research areas concerning VoD often focus on increasing the throughput and reliability of single server, but rarely addresses the smooth provision of service during server as well as network failures. Reliable Server Pooling (RSerPool), being capable of providing high availability by using multiple redundant servers as single source point, can be a solution to overcome the above failures. During a possible server failure, the continuity of service is retained by another server. In order to achieve transparent failover, efficient state sharing is an important requirement. In this paper, we present an elegant, simple, efficient and scalable approach which has been developed to facilitate the transfer of state by the client itself, using extended cookie mechanism, which ensures that there is no noticeable change in disruption or the video quality.

Auxin-Responsive OsMGH3, a Common Downstream Target of OsMADS1 and OsMADS6, Controls Rice Floret Fertility

GH3 proteins control auxin homeostasis by inactivating excess auxin as conjugates of amino acids and sugars and thereby controlling cellular bioactive auxin. Since auxin regulates many aspects of plant growth and development, regulated expression of these genes offers a mechanism to control various developmental processes. OsMGH3/OsGH3-8 is expressed abundantly in rice florets and is regulated by two related and redundant transcription factors, OsMADS1 and OsMADS6, but its contribution to flower development is not known. We functionally characterize OsMGH3 by overexpression and knock-down analysis and show a partial overlap in these phenotypes with that of mutants in OsMADS1 and OsMADS6. The overexpression of OsMGH3 during the vegetative phase affects the overall plant architecture, whereas its inflorescence-specific overexpression creates short panicles with reduced branching, resembling in part the effects of OsMADS1 overexpression. In contrast, the down-regulation of endogenous OsMGH3 caused phenotypes consistent with auxin overproduction or activated signaling, such as ectopic rooting from aerial nodes. Florets in OsMGH3 knock-down plants were affected in carpel development and pollen viability, both of which reduced fertility. Some of these floret phenotypes are similar to osmads6 mutants. Taken together, we provide evidence for the functional significance of auxin homeostasis and its transcriptional regulation during rice panicle branching and floret organ development.

The beta-Glucoside (bgl) Operon of Escherichia coli Is Involved in the Regulation of oppA, Encoding an Oligopeptide Transporter

We report that the bgl operon of Escherichia coli, encoding the functions necessary for the uptake and metabolism of aryl-beta-glucosides, is involved in the regulation of oligopeptide transport during stationary phase. Global analysis of intracellular proteins from Bgl-positive (Bgl(+)) and Bgl-negative (Bgl(-)) strains revealed that the operon exerts regulation on at least 12 downstream target genes. Of these, oppA, which encodes an oligopeptide transporter, was confirmed to be upregulated in the Bgl(+) strain. Loss of oppA function results in a partial loss of the growth advantage in stationary-phase (GASP) phenotype of Bgl(+) cells. The regulatory effect of the bgl operon on oppA expression is indirect and is mediated via gcvA, the activator of the glycine cleavage system, and gcvB, which regulates oppA at the posttranscriptional level. We show that BglG destabilizes the gcvA mRNA in vivo, leading to reduced expression of gcvA in the stationary phase. Deletion of gcvA results in the downregulation of gcvB and upregulation of oppA and can partially rescue the loss of the GASP phenotype seen in Delta bglG strains. A possible mechanism by which oppA confers a competitive advantage to Bgl(+) cells relative to Bgl(-) cells is discussed.

The Structure of the Thioredoxin-Triosephosphate Isomerase Complex Provides Insights into the Reversible Glutathione-Mediated Regulation of Triosephosphate Isomerase

Protein-protein interactions are crucial for many biological functions. The redox interactome encompasses numerous weak transient interactions in which thioredoxin plays a central role. Proteomic studies have shown that thioredoxin binds to numerous proteins belonging to various cellular processes, including energy metabolism. Thioredoxin has cross talk with other redox mechanisms involving glutathionylation and has functional overlap with glutaredoxin in deglutathionylation reactions. In this study, we have explored the structural and biochemical interactions of thioredoxin with the glycolytic enzyme, triosephosphate isomerase. Nuclear magnetic resonance chemical shift mapping methods and molecular dynamics-based docking have been applied in deriving a structural model of the thioredoxin-triosephosphate isomerase complex. The spatial proximity of active site cysteine residues of thioredoxin to reactive thiol groups on triosephosphate isomerase provides a direct link to the observed deglutathionylation of cysteine 217 in triosephosphate isomerase, thereby reversing the inhibitory effect of S-glutathionylation of triosephosphate isomerase.

The Structure of the Thioredoxin−Triosephosphate Isomerase Complex Provides Insights into the Reversible Glutathione-Mediate Regulation of Triosephosphate Isomerase

Protein−protein interactions are crucial for many biological functions. The redox interactome encompasses numerous weak transient interactions in which thioredoxin plays a central role. Proteomic studies have shown that thioredoxin binds to numerous proteins belonging to various cellular processes, including energy metabolism. Thioredoxin has cross talk with other redox mechanisms involving glutathionylation and has functional overlap with glutaredoxin in deglutathionylation reactions. In this study, we have explored the structural and biochemical interactions of thioredoxin with the glycolytic enzyme, triosephosphate isomerase. Nuclear magnetic resonance chemical shift mapping methods and molecular dynamics-based docking have been applied in deriving a structural model of the thioredoxin−triosephosphate isomerase complex. The spatial proximity of active site cysteine residues of thioredoxin to reactive thiol groups on triosephosphate isomerase provides a direct link to the observed deglutathionylation of cysteine 217 in triosephosphate isomerase, thereby reversing the inhibitory effect of S-glutathionylation of triosephosphate isomerase.

Functional regulation of PVBV Nuclear Inclusion protein-a protease activity upon interaction with Viral Protein genome-linked and phosphorylation

Regulation of NIa-Pro is crucial for polyprotein processing and hence, for successful infection of potyviruses. We have examined two novel mechanisms that could regulate NIa-Pro activity. Firstly, the influence of VPg domain on the proteolytic activity of NIa-Pro was investigated. It was shown that the turnover number of the protease increases when these two domains interact (as: two-fold; trans: seven-fold) with each other. Secondly, the protease activity of NIa-Pro could also be modulated by phosphorylation at Ser129. A mutation of this residue either to aspartate (phosphorylation-mimic) or alanine (phosphorylation-deficient) drastically reduces the protease activity. Based on these observations and molecular modeling studies, we propose that interaction with VPg as well as phosphorylation of Ser129 could relay a signal through Trp143 present at the protein surface to the active site pocket by subtle conformational changes, thus modulating protease activity of NIa-Pro. (C) 2011 Elsevier Inc. All rights reserved.

Performance modeling and architecture exploration of network processors

This paper proposes a Petri net model for a commercial network processor (Intel iXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, network address translation, and IP security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.