Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

An 8x8 thermopile based uncooled infrared sensor

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Comparação do controle do inversor trifásico conectado à rede com filtro LCL considerando o amortecimento passivo e ativo

Distributed generation systems must fulfill standards specifications of current harmonics injected to the grid. In order to satisfy these grid requirements, passive filters are connected between inverter and grid. This work compares the characteristic response of the traditional inductive (L) filter with the inductive-capacitive-inductive (LCL) filter. It is shown that increasing the inductance L leads to a good ripple current suppression around the inverter switching frequency. The LCL filter provides better harmonic attenuation and reduces the filter size. The main drawback is the LCL filter impedance, which is characterized by a typical resonance peak, which must be damped to avoid instability. Passive or active techniques can be used to damp the LCL resonance. To address this issue, this dissertation presents a comparison of current control for PV grid-tied inverters with L filter and LCL filter and also discuss the use of active and passive damping for different regions of resonance frequency. From the mathematical models, a design methodology of the controllers was developed and the dynamic behavior of the system operating in closed loop was investigated. To validate the studies developed during this work, experimental results are presented using a three-phase 5kW experimental platform. The main components and their functions are discussed in this work. Experimental results are given to support the theoretical analysis and to illustrate the performance of grid-connected PV inverter system. It is shown that the resonant frequency of the system, and sampling frequency can be associated in order to calculate a critical frequency, below which is essential to perform the damping of the LCL filter. Also, the experimental results show that the active buffer per virtual resistor, although with a simple development, is effective to damp the resonance of the LCL filter and allow the system to operate stable within predetermined parameters.

Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling

Substrate current injection is the origin of external latchup and substrate noise coupling. The trigger current for external latchup depends on the duration of the trigger event. A physics-based model is provided to model the effects of aggressor to victim spacing and orientation on transient triggering of external latchup. The latchup susceptibility of standard cell based designs is also investigated. Guard rings are used to reduce latchup susceptibility and to reduce the substrate noise coupled to sensitive analog circuits. In this work, the effectiveness of different guard ring topologies for the reduction of substrate noise coupling is also investigated.

Holistic Design In High-Speed Optical Interconnects

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Materials design for ambipolar devices: tuning orbital energetics in oligothiophene-naphthalimides semiconductors

Ambipolar organic field-effect transistors (OFETs), which can efficiently transport both holes and electrons, using a single type of electrode, are currently of great interest due to their possible applications in complementary metal oxide semiconductor (CMOS)-like circuits, sensors, and in light-emitting transistors. Several theoretical and experimental studies have argued that most organic semiconductors should be able to transport both types of carrier, although typically unipolar behavior is observed. One factor that can compromise ambipolar transport in organic semiconductors is poor solid state overlap between the HOMO (p-type) or LUMO (n-type) orbitals of neighboring molecules in the semiconductor thin film. In the search of low-bandgap ambipolar materials, where the absence of skeletal distortions allows closer intermolecular π-π stacking and enhanced intramolecular π-conjugation, a new family of oligothiophene-naphthalimide assemblies have been synthesized and characterized, in which both donor and acceptor moieties are directly conjugated through rigid linkers. In previous works we found that oligothiophene-napthalimide assemblies connected through amidine linkers (NDI derivates) exhibit skeletal distortions (50-60º) arising from steric hindrance between the carbonyl group of the arylene core and the sulphur atom of the neighbored thiophene ring (see Figure 1). In the present work we report novel oligo- and polythiophene–naphthalimide analogues NAI-3T, NAI-5T and poly-NAI-8C-3T, in which the connections of the amidine linkage have been inverted in order to prevent steric interactions. Thus, the nitrogen atoms are directly connected to the naphthalene moiety in NAI derivatives while they were attached directly to the thiophene moiety in the previously investigated NDI-3T and NDI-5T. In Figure 1 is depicted the calculated molecular structure of NAI-3T together with that of NDI-3T showing how the steric interactions are not present in the novel NAI derivative. The planar skeletons in these new family induce higher degree of crystallinity and the carrier charge transport can be switched from n-type to ambipolar behaviour. The highest FET performance is achieved for vapor-deposited films of NAI-3T with mobilities of 1.95x10-4cm2V-1s-1 and 2.00x10-4cm2V-1s-1 for electrons and holes, respectively. Finally, these planar semiconductors are compared with their NDI derivates analogues, which exhibit only n-type mobility, in order to understand the origin of the ambipolarity in this new series of molecular semiconductors.

Electro-optical characterization of IC compatible microcantilevers

The aim of this work is to simulate and optically characterize the piezoelectric performance of complementary metal oxide semiconductor (CMOS) compatible microcantilevers based on aluminium nitride (AlN) and manufactured at room temperature. This study should facilitate the integration of piezoelectric micro-electro-mechanical systems (MEMS) such as microcantilevers, in CMOS technology. Besides compatibility with standard integrated circuit manufacturing procedures, low temperature processing also translates into higher throughput and, as a consequence, lower manufacturing costs. Thus, the use of the piezoelectric properties of AlN manufactured by reactive sputtering at room temperature is an important step towards the integration of this type of devices within future CMOS technology standards. To assess the reliability of our fabrication process, we have manufactured arrays of free-standing microcantilever beams of variable dimension and studied their piezoelectric performance. The characterization of the first out-of-plane modes of AlN-actuated piezoelectric microcantilevers has been carried out using two optical techniques: laser Doppler vibrometry (LDV) and white light interferometry (WLI). In order to actuate the cantilevers, a periodic chirp signal in certain frequency ranges was applied between the device electrodes. The nature of the different vibration modes detected has been studied and compared with that obtained by a finite element model based simulation (COMSOL Multiphysics), showing flexural as well as torsional modes. The correspondence between theoretical and experimental data is reasonably good, probing the viability of this high throughput and CMOS compatible fabrication process. To complete the study, X-ray diffraction as well as d33 piezoelectric coefficient measurements were also carried out.

Silicon Photonic Device for Wavelength Sensing and Monitoring

Over the last decade advances and innovations from Silicon Photonics technology were observed in the telecommunications and computing industries. This technology which employs Silicon as an optical medium, relies on current CMOS micro-electronics fabrication processes to enable medium scale integration of many nano-photonic devices to produce photonic integrated circuitry. However, other fields of research such as optical sensor processing can benefit from silicon photonics technology, specially in sensors where the physical measurement is wavelength encoded. In this research work, we present a design and application of a thermally tuned silicon photonic device as an optical sensor interrogator. The main device is a micro-ring resonator filter of 10 $\mu m$ of diameter. A photonic design toolkit was developed based on open source software from the research community. With those tools it was possible to estimate the resonance and spectral characteristics of the filter. From the obtained design parameters, a 7.8 x 3.8 mm optical chip was fabricated using standard micro-photonics techniques. In order to tune a ring resonance, Nichrome micro-heaters were fabricated on top of the device. Some fabricated devices were systematically characterized and their tuning response were determined. From measurements, a ring resonator with a free-spectral-range of 18.4 nm and with a bandwidth of 0.14 nm was obtained. Using just 5 mA it was possible to tune the device resonance up to 3 nm. In order to apply our device as a sensor interrogator in this research, a model of wavelength estimation using time interval between peaks measurement technique was developed and simulations were carried out to assess its performance. To test the technique, an experiment using a Fiber Bragg grating optical sensor was set, and estimations of the wavelength shift of this sensor due to axial strains yield an error within 22 pm compared to measurements from spectrum analyzer. Results from this study implies that signals from FBG sensors can be processed with good accuracy using a micro-ring device with the advantage of ts compact size, scalability and versatility. Additionally, the system also has additional applications such as processing optical wavelength shifts from integrated photonic sensors and to be able to track resonances from laser sources.

Hybrid Power System Intelligent Operation and Protection Involving Distributed Architectures and Pulsed Loads

Efficient and reliable techniques for power delivery and utilization are needed to account for the increased penetration of renewable energy sources in electric power systems. Such methods are also required for current and future demands of plug-in electric vehicles and high-power electronic loads. Distributed control and optimal power network architectures will lead to viable solutions to the energy management issue with high level of reliability and security. This dissertation is aimed at developing and verifying new techniques for distributed control by deploying DC microgrids, involving distributed renewable generation and energy storage, through the operating AC power system. To achieve the findings of this dissertation, an energy system architecture was developed involving AC and DC networks, both with distributed generations and demands. The various components of the DC microgrid were designed and built including DC-DC converters, voltage source inverters (VSI) and AC-DC rectifiers featuring novel designs developed by the candidate. New control techniques were developed and implemented to maximize the operating range of the power conditioning units used for integrating renewable energy into the DC bus. The control and operation of the DC microgrids in the hybrid AC/DC system involve intelligent energy management. Real-time energy management algorithms were developed and experimentally verified. These algorithms are based on intelligent decision-making elements along with an optimization process. This was aimed at enhancing the overall performance of the power system and mitigating the effect of heavy non-linear loads with variable intensity and duration. The developed algorithms were also used for managing the charging/discharging process of plug-in electric vehicle emulators. The protection of the proposed hybrid AC/DC power system was studied. Fault analysis and protection scheme and coordination, in addition to ideas on how to retrofit currently available protection concepts and devices for AC systems in a DC network, were presented. A study was also conducted on the effect of changing the distribution architecture and distributing the storage assets on the various zones of the network on the system’s dynamic security and stability. A practical shipboard power system was studied as an example of a hybrid AC/DC power system involving pulsed loads. Generally, the proposed hybrid AC/DC power system, besides most of the ideas, controls and algorithms presented in this dissertation, were experimentally verified at the Smart Grid Testbed, Energy Systems Research Laboratory. All the developments in this dissertation were experimentally verified at the Smart Grid Testbed.

Flexible Power Control of Photovoltaic Plants Connected to Distribution Networks

This paper presents a system to control the power injected by a photovoltaic (PV) plant on the receiving network. This control is intended to mitigate some of the negative impacts that these units may produce on such networks, while increasing the installed power of the plant. The controlled parameters are the maximum allowed value of injected active power and the corresponding power factor, whose setpoints values may be fixed or dynamic. The developed system allows a local and a remote control. The injected power and the corresponding power factor may be set by following a predetermined profile or by real time adjustments to fulfill specific operation constraints on the receiving network. The system acts by adjusting the control parameters on the PV inverters. The main goal of the system is, in the end, to control the PV plant, ensuring the accomplishment of technical constraints and, at the same time, maximizing the installed power of the PV plant, which may be an important issue concerning the economic performance of such plants

High Frequency Class DE Converter Using a Multilayer Coreless PCB Transformer

In modern power electronics equipment, it is desirable to design a low profile, high power density, and fast dynamic response converter. Increases in switching frequency reduce the size of the passive components such as transformers, inductors, and capacitors which results in compact size and less requirement for the energy storage. In addition, the fast dynamic response can be achieved by operating at high frequency. However, achieving high frequency operation while keeping the efficiency high, requires new advanced devices, higher performance magnetic components, and new circuit topology. These are required to absorb and utilize the parasitic components and also to mitigate the frequency dependent losses including switching loss, gating loss, and magnetic loss. Required performance improvements can be achieved through the use of Radio Frequency (RF) design techniques. To reduce switching losses, resonant converter topologies like resonant RF amplifiers (inverters) combined with a rectifier are the effective solution to maintain high efficiency at high switching frequencies through using the techniques such as device parasitic absorption, Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), and a resonant gating. Gallium Nitride (GaN) device technologies are being broadly used in RF amplifiers due to their lower on- resistance and device capacitances compared with silicon (Si) devices. Therefore, this kind of semiconductor is well suited for high frequency power converters. The major problems involved with high frequency magnetics are skin and proximity effects, increased core and copper losses, unbalanced magnetic flux distribution generating localized hot spots, and reduced coupling coefficient. In order to eliminate the magnetic core losses which play a crucial role at higher operating frequencies, a coreless PCB transformer can be used. Compared to the conventional wire-wound transformer, a planar PCB transformer in which the windings are laid on the Printed Board Circuit (PCB) has a low profile structure, excellent thermal characteristics, and ease of manufacturing. Therefore, the work in this thesis demonstrates the design and analysis of an isolated low profile class DE resonant converter operating at 10 MHz switching frequency with a nominal output of 150 W. The power stage consists of a class DE inverter using GaN devices along with a sinusoidal gate drive circuit on the primary side and a class DE rectifier on the secondary side. For obtaining the stringent height converter, isolation is provided by a 10-layered coreless PCB transformer of 1:20 turn’s ratio. It is designed and optimized using 3D Finite Element Method (FEM) tools and radio frequency (RF) circuit design software. Simulation and experimental results are presented for a 10-layered coreless PCB transformer operating in 10 MHz.