Artifact-free reconstruction from off-axis digital holograms through nonlinear filtering

We present experimental investigation of a new reconstruction method for off-axis digital holographic microscopy (DHM). This method effectively suppresses the object auto-correlation, commonly called the zero-order term, from holographic measurements, thereby suppressing the artifacts generated by the intensities of the two beams employed for interference from complex wavefield reconstruction. The algorithm is based on non-linear filtering, and can be applied to standard DHM setups, with realistic recording conditions. We study the applicability of the technique under different experimental configurations, such as topographic images of microscopic specimens or speckle holograms.

Optimization of off-oriented Ge substrates for MOVPE-grown GaAs solar cells

GaAs/Ge heterostructures having abrupt interfaces were grown on 2degrees, 6degrees, and 9degrees off-cut Ge substrates and investigated by cross-sectional high-resolution transmission electron microscopy (HRTEM), scanning electron microscopy, photoluminescence spectroscopy and electrochemical capacitance voltage (ECV) profiler. The GaAs films were grown on off-oriented Ge substrates with growth temperature in the range of 600-700degreesC, growth rate of 3-12 mum/hr and a V/III ratio of 29-88. The lattice indexing of HRTEM exhibits an excellent lattice line matching between GaAs and Ge substrate. The PL spectra from GaAs layer on 6degrees off-cut Ge substrate shows the higher excitonic peak compared with 2degrees and 9degrees off-cut Ge substrates. In addition, the luminescence intensity from the GaAs solar cell grown on 6degrees off-cut is higher than on 9degrees off-cut Ge substrates and signifies the potential use of 6degrees off-cut Ge substrate in the GaAs solar cells industry. The ECV profiling shows an abrupt film/substrate interface as well as between various layers of the solar cell structures.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Aromatic, microporous polymer networks with high surface area generated in Friedel-Crafts-type polycondensations

A series of novel, microporous polymer networks (MPNs) have been generated in a simple, acid catalysed Friedel-Crafts-type self-condensation of A(2)B(2)- and A(2)B(4)-type fluorenone monomers. Two A2B4-type monomers with 2,7-bis(N, N-diphenylamino) A or 2,7-bis [4-(N, N-diphenylamino) phenyl] D substitution of the fluorenone cores lead to MPNs with high S(BET) surface areas of up to 1400 m(2) g(-1). Two MPNs made of binary monomer mixtures showed the highest Brunauer-Emmett-Teller (BET) surface areas S(BET) of our series (SBET of up to 1800 m(2) g(-1)) after washing the powdery samples with supercritical carbon dioxide. Total pore volumes of up to 1.6 cm(3) g(-1) have been detected. It is observed that the substitution pattern of the monomers is strongly influencing the resulting physicochemical properties of the microporous polymer networks (MPNs).

Present status of Gottigere Tank : Indicator of Decision maker’s apathy

Gottigere lake with a water spread area of about 14.98 ha is located in the Bellandur Lake catchment of the South Pennar River basin. In recent years, this lake catchment has been subjected to environmental stress mainly due to the rampant unplanned developmental activities in the catchment. The functional ability of the ecosystem is impaired due to structural changes in the ecosystem. This is evident from poor water quality, breeding of disease vectors, contamination of groundwater in the catchment, frequent flooding in the catchment due to topography alteration, decline in groundwater table, erosion in lake bed, etc. The development plans of the region (current as well as the proposed) ignore the integrated planning approaches considering all components of the ecosystem. Serious threats to the sustainability of the region due to lack of holistic approaches in aquatic resources management are land use changes (removal of vegetation cover, etc.), point and non-point sources of pollution impairing water quality, dumping of solid waste (building waste, etc.). Conservation of lake ecosystem is possible only when the physical and chemical integrity of its catchment is maintained. Alteration in the catchment either due to land use changes (leading to paved surface area from vegetation cover), alteration in topography, construction of roads in the immediate vicinity are detrimental to water yield in the catchment and hence, the sustenance of the lake. Open spaces in the form of lakes and parks aid as kidney and lung in an urban ecosystem, which maintain the health of the people residing in the locality. Identification of core buffer zones and conservation of buffer zones (500 to 1000 m from shore) is to be taken up on priority for conservation and sustainable management of Bangalore lakes. Bangalore is located over a ridge delineating four watersheds, viz. Hebbal, Koramangala, Challaghatta and Vrishabhavathi. Lakes and tanks are an integral part of natural drainage and help in retaining water during rainfall, which otherwise get drained off as flash floods. Each lake harvests rainwater from its catchment and surplus flows downstream spilling into the next lake in the chain. The topography of Bangalore has uniquely supported the creation of a large number of lakes. These lakes form chains, being a series of impoundments across streams. This emphasises the interconnectivity among Bangalore lakes, which has to be retained to prevent Bangalore from flooding or from water scarcity. The main source of replenishment of groundwater is the rainfall. The slope of the terrain allows most of the rainwater to flow as run-off. With the steep gradients available in the major valleys of Bangalore, the rainwater will flow out of the city within four to five hours. Only a small fraction of the rainwater infiltrates into the soil. The infiltration of water into the subsoil has declined with more and more buildings and paved road being constructed in the city. Thus the natural drainage of Bangalore is governed by flows from the central ridge to all lower contours and is connected with various tanks and ponds. There are no major rivers flowing in Bangalore and there is an urgent need to sustain these vital ecosystems through proper conservation and management measures. The proposed peripheral ring road connecting Hosur Road (NH 7) and Mysore Road (SH 17) at Gottigere lake falls within the buffer zone of the lake. This would alter the catchment integrity and hence water yield affecting flora, fauna and local people, and ultimately lead to the disappearance of Gottigere lake. Developmental activities in lake catchments, which has altered lake’s ecological integrity is in violation of the Indian Fisheries Act – 1857, the Indian Forest Act – 1927, Wildlife (Protection) Act – 1972, Water (Prevention and Control of Pollution) Act – 1974, Water (Prevention and Control of Pollution) Act – 1977, Forest (Conservation Act) – 1980, Environmental (Protection) Act – 1986, Wildlife (Protection) Amendment Act – 1991 and National Conservation Strategy and Policy Statement on Environment and Development – 1992. Considering 65% decline of waterbodies in Bangalore (during last three decades), decision makers should immediately take preventive measures to ensure that lake ecosystems are not affected. This report discusses the impacts due to the proposed infrastructure developmental activities in the vicinity of Gottigere tank.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer

H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.