Análise do desempenho térmico de construções: projeto e soluções alternativas

O presente Relatório de Estágio representa o último passo para a obtenção do Grau de Mestre em Engenharia Civil – Ramo de Construções, lecionado no Instituto Superior de Engenharia do Porto (ISEP). Este relatório refere-se ao trabalho desenvolvido em estágio na entidade acolhedora Concexec – Arquitetura, Lda., através da elaboração e desenvolvimento dos projetos de térmica de edifícios referentes a duas moradias unifamiliares. Os referidos projetos foram elaborados em colaboração com a entidade patronal do estágio, precedidos de visitas aos locais das respetivas obras e análise dos respetivos projetos de especialidades considerados relevantes. Numa primeira parte do relatório está descrita a realidade da situação energética atual em Portugal, sucedida da referência e descrição de soluções construtivas disponíveis no mercado nacional que visam a melhoria da eficiência energética em edifícios de habitação. Numa segunda parte do relatório encontram-se descritos, de uma forma detalhada, os projetos de térmica de edifícios referidos e respetivas soluções alternativas, sucedidos de uma análise energética e económica que permita deduzir qual a melhor solução a ser aplicada mediante o caso. Os resultados obtidos cumpriram com todos os requisitos regulamentares estabelecidos, permitindo obter conclusões adequadas ao âmbito do presente Relatório de Estágio, cumprindo, desta forma, os objetivos que lhe foram estabelecidos. No final estão descritas as conclusões que foram obtidas durante todo o processo de pesquisa e desenvolvimento do estágio realizado.

Classificação de sons cardíacos usando Motifs: desenvolvimento de uma aplicação móvel

Este documento foi redigido no âmbito da Tese, do Mestrado em Engenharia Informática na área de Tecnologias do Conhecimento e Decisão, do Departamento de Engenharia Informática, do ISEP, cujo tema é classificação de sons cardíacos usando motifs. Neste trabalho, apresenta-se um algoritmo de classificação de sons cardíacos, capaz de identificar patologias cardíacas. A classificação do som cardíaco é um trabalho desafiante dada a dificuldade em separar os sons ambiente (vozes, respiração, contacto do microfone com superfícies como pele ou tecidos) ou de ruído dos batimentos cardíacos. Esta abordagem seguiu a metodologia de descoberta de padrões SAX (motifs) mais frequentes, em séries temporais relacionando-os com a ocorrência sistólica (S1) e a ocorrência diastólica (S2) do coração. A metodologia seguida mostrou-se eficaz a distinguir sons normais de sons correspondentes a patologia. Os resultados foram publicados na conferência internacional IDEAS’14 [Oliveira, 2014], em Julho deste ano. Numa fase seguinte, desenvolveu-se uma aplicação móvel, capaz de captar os batimentos cardíacos, de os tratar e os classificar. A classificação dos sons é feita usando o método referido no parágrafo anterior. A aplicação móvel, depois de tratar os sons, envia-os para um servidor, onde o programa de classificação é executado, e recebe a resposta da classificação. É também descrita a arquitetura aplicacional desenhada e as componentes que a constituem, as ferramentas e tecnologias utilizadas.

Intra-Task Device Scheduling for Real-Time Embedded Systems

An ever increasing need for extra functionality in a single embedded system demands for extra Input/Output (I/O) devices, which are usually connected externally and are expensive in terms of energy consumption. To reduce their energy consumption, these devices are equipped with power saving mechanisms. While I/O device scheduling for real-time (RT) systems with such power saving features has been studied in the past, the use of energy resources by these scheduling algorithms may be improved. Technology enhancements in the semiconductor industry have allowed the hardware vendors to reduce the device transition and energy overheads. The decrease in overhead of sleep transitions has opened new opportunities to further reduce the device energy consumption. In this research effort, we propose an intra-task device scheduling algorithm for real-time systems that wakes up a device on demand and reduces its active time while ensuring system schedulability. This intra-task device scheduling algorithm is extended for devices with multiple sleep states to further minimise the overall device energy consumption of the system. The proposed algorithms have less complexity when compared to the conservative inter-task device scheduling algorithms. The system model used relaxes some of the assumptions commonly made in the state-of-the-art that restrict their practical relevance. Apart from the aforementioned advantages, the proposed algorithms are shown to demonstrate the substantial energy savings.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors

6th International Real-Time Scheduling Open Problems Seminar (RTSOPS 2015), Lund, Sweden.

Towards Certifiable Multicore-based Platforms for Avionics

Work in Progress Session, 21st IEEE Real-Time and Embedded Techonology and Applications Symposium (RTAS 2015). 13 to 16, Apr, 2015, pp 27-28. Seattle, U.S.A..

Allocation of Parallel Real-Time Tasks in Distributed Multi-core Architectures supported by an FTT-SE Network

Distributed real-time systems such as automotive applications are becoming larger and more complex, thus, requiring the use of more powerful hardware and software architectures. Furthermore, those distributed applications commonly have stringent real-time constraints. This implies that such applications would gain in flexibility if they were parallelized and distributed over the system. In this paper, we consider the problem of allocating fixed-priority fork-join Parallel/Distributed real-time tasks onto distributed multi-core nodes connected through a Flexible Time Triggered Switched Ethernet network. We analyze the system requirements and present a set of formulations based on a constraint programming approach. Constraint programming allows us to express the relations between variables in the form of constraints. Our approach is guaranteed to find a feasible solution, if one exists, in contrast to other approaches based on heuristics. Furthermore, approaches based on constraint programming have shown to obtain solutions for these type of formulations in reasonable time.

A framework for using real data with distributed low cost sensors

Currently, due to the widespread use of computers and the internet, students are trading libraries for the World Wide Web and laboratories with simulation programs. In most courses, simulators are made available to students and can be used to proof theoretical results or to test a developing hardware/product. Although this is an interesting solution: low cost, easy and fast way to perform some courses work, it has indeed major disadvantages. As everything is currently being done with/in a computer, the students are loosing the “feel” of the real values of the magnitudes. For instance in engineering studies, and mainly in the first years, students need to learn electronics, algorithmic, mathematics and physics. All of these areas can use numerical analysis software, simulation software or spreadsheets and in the majority of the cases data used is either simulated or random numbers, but real data could be used instead. For example, if a course uses numerical analysis software and needs a dataset, the students can learn to manipulate arrays. Also, when using the spreadsheets to build graphics, instead of using a random table, students could use a real dataset based, for instance, in the room temperature and its variation across the day. In this work we present a framework which uses a simple interface allowing it to be used by different courses where the computers are the teaching/learning process in order to give a more realistic feeling to students by using real data. A framework is proposed based on a set of low cost sensors for different physical magnitudes, e.g. temperature, light, wind speed, which are connected to a central server, that the students have access with an Ethernet protocol or are connected directly to the student computer/laptop. These sensors use the communication ports available such as: serial ports, parallel ports, Ethernet or Universal Serial Bus (USB). Since a central server is used, the students are encouraged to use sensor values results in their different courses and consequently in different types of software such as: numerical analysis tools, spreadsheets or simply inside any programming language when a dataset is needed. In order to do this, small pieces of hardware were developed containing at least one sensor using different types of computer communication. As long as the sensors are attached in a server connected to the internet, these tools can also be shared between different schools. This allows sensors that aren't available in a determined school to be used by getting the values from other places that are sharing them. Another remark is that students in the more advanced years and (theoretically) more know how, can use the courses that have some affinities with electronic development to build new sensor pieces and expand the framework further. The final solution provided is very interesting, low cost, simple to develop, allowing flexibility of resources by using the same materials in several courses bringing real world data into the students computer works.

A Real Time Vision System for Autonomous Systems: Characterization during a Middle Size Match

in RoboCup 2007: Robot Soccer World Cup XI

ROAZ and ROAZ II Autonomous Surface Vehicle Design and Implementation

International Lifesaving Congress 2007, La Coruna, Spain, December, 2007

ROAZ Autonomous Surface Vehicle Design and Implementation

The design of an Autonomous Surface Vehicle for operation in river and estuarine scenarios is presented. Multiple operations with autonomous underwater vehicles and support to AUV missions are one of the main design goals in the ROAZ system. The mechanical design issues are discussed. Hardware, software and implementation status are described along with the control and navigation system architecture. Some preliminary test results concerning a custom developed thruster are presented along with hydrodynamic drag calculations by the use of computer fluid dynamic methods.

ISePorto Robotic Soccer Team: A New Player Generation

Proceedings of the Scientific Meeting of the Portuguese Robotics Open 2004

Towards the Certification of Multicore Platforms in the Avionics Domain

Poster presented in Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.

Utilização de GPGPUs para a identificação de objectos em imagens tomográficas

Dissertação para obtenção do Grau de Mestre em Engenharia Informática