994 resultados para soft-commutation technique
Resumo:
Changes occurring in the viability of Salmonella enterica subsp. enterica during the preparation and cold storage of Domiati cheese, Kariesh cheese and ice-cream were examined. A significant decrease in numbers was observed after whey drainage during the manufacture of Domiati cheese, but Salmonella remained viable for 13 weeks in cheeses prepared from milks with between 60 and 100 g/L NaCl; the viability declined in Domiati cheese made from highly salted milk during the later stages of storage. The method of coagulation used in the preparation of Kariesh cheese affected the survival time of the pathogen, and it varied from 2 to 3 weeks in cheeses made with a slow-acid coagulation method to 4-5 weeks for an acid-rennet coagulation method. This difference was attributed to the higher salt-in-moisture levels and lower pH values of Kariesh cheese prepared by the slow-acid coagulation method. A slight decrease in the numbers of Salmonella resulted from ageing ice-cream mix for 24 h at 0degreesC, but a greater reduction was evident after one day of frozen storage at -20degreesC. The pathogen survived further frozen storage for four months without any substantial change in numbers.
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The incorporation of caseins and whey proteins into acid gels produced from unheated and heat treated skimmed milk was studied by confocal scanning laser microscopy (CSLM) using fluorescent labelled proteins. Bovine casein micelles were labelled using Alexa Fluor 594, while whey proteins were labelled using Alexa Fluor 488. Samples of the labelled protein solutions were introduced into aliquots of pasteurised skim milk, and skim milk heated to 90 degrees C for 2 min and 95 degrees C for 8 min. The milk was acidified at 40 degrees C to a final pH of 4.4 using 20 g gluconodelta-lactone/l (GDL). The formation of gels was observed with CSLM at two wavelengths (488 nm and 594 nm), and also by visual and rheological methods. In the control milk, as pH decreased distinct casein aggregates appeared, and as further pH reduction occurred, the whey proteins could be seen to coat the casein aggregates. With the heated milks, the gel structure was formed of continuous strands consisting of both casein and whey protein. The formation of the gel network was correlated with an increase in the elastic modulus for all three treatments, in relation to the severity of heat treatment. This model system allows the separate observation of the caseins and whey proteins, and the study of the interactions between the two protein fractions during the formation of the acid gel structure, on a real-time basis. The system could therefore be a valuable tool in the study of structure formation in yoghurt and other dairy protein systems.
Resumo:
Introduction A high saturated fatty acid intake is a well recognized risk factor for coronary heart disease development. More recently a high intake of n-6 polyunsaturated fatty acids (PUFA) in combination with a low intake of the long chain n-3 PUFA, eicosapentaenoic acid and docosahexaenoic acid has also been implicated as an important risk factor. Aim To compare total dietary fat and fatty acid intake measured by chemical analysis of duplicate diets with nutritional database analysis of estimated dietary records, collected over the same 3-day study period. Methods Total fat was analysed using soxhlet extraction and subsequently the individual fatty acid content of the diet was determined by gas chromatography. Estimated dietary records were analysed using a nutrient database which was supplemented with a selection of dishes commonly consumed by study participants. Results Bland & Altman statistical analysis demonstrated a lack of agreement between the two dietary assessment techniques for determining dietary fat and fatty acid intake. Conclusion The lack of agreement observed between dietary evaluation techniques may be attributed to inadequacies in either or both assessment techniques. This study highlights the difficulties that may be encountered when attempting to accurately evaluate dietary fat intake among the population.
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Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed Control circuits using a synchronous, a semi-synchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.
Resumo:
Very large scale scheduling and planning tasks cannot be effectively addressed by fully automated schedule optimisation systems, since many key factors which govern 'fitness' in such cases are unformalisable. This raises the question of an interactive (or collaborative) approach, where fitness is assigned by the expert user. Though well-researched in the domains of interactively evolved art and music, this method is as yet rarely used in logistics. This paper concerns a difficulty shared by all interactive evolutionary systems (IESs), but especially those used for logistics or design problems. The difficulty is that objective evaluation of IESs is severely hampered by the need for expert humans in the loop. This makes it effectively impossible to, for example, determine with statistical confidence any ranking among a decent number of configurations for the parameters and strategy choices. We make headway into this difficulty with an Automated Tester (AT) for such systems. The AT replaces the human in experiments, and has parameters controlling its decision-making accuracy (modelling human error) and a built-in notion of a target solution which may typically be at odds with the solution which is optimal in terms of formalisable fitness. Using the AT, plausible evaluations of alternative designs for the IES can be done, allowing for (and examining the effects of) different levels of user error. We describe such an AT for evaluating an IES for very large scale planning.
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The General Packet Radio Service (GPRS) has been developed for the mobile radio environment to allow the migration from the traditional circuit switched connection to a more efficient packet based communication link particularly for data transfer. GPRS requires the addition of not only the GPRS software protocol stack, but also more baseband functionality for the mobile as new coding schemes have be en defined, uplink status flag detection, multislot operation and dynamic coding scheme detect. This paper concentrates on evaluating the performance of the GPRS coding scheme detection methods in the presence of a multipath fading channel with a single co-channel interferer as a function of various soft-bit data widths. It has been found that compressing the soft-bit data widths from the output of the equalizer to save memory can influence the likelihood decision of the coding scheme detect function and hence contribute to the overall performance loss of the system. Coding scheme detection errors can therefore force the channel decoder to either select the incorrect decoding scheme or have no clear decision which coding scheme to use resulting in the decoded radio block failing the block check sequence and contribute to the block error rate. For correct performance simulation, the performance of the full coding scheme detection must be taken into account.
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This paper discusses the architectural design, implementation and associated simulated peformance results of a possible receiver solution fir a multiband Ultra-Wideband (UWB) receiver. The paper concentrates on the tradeoff between the soft-bit width and numerical precision requirements for the receiver versus performance. The required numerical precision results obtained in this paper can be used by baseband designers of cost effective UWB systems using Systein-on-Chip (SoC), FPGA and ASIC technology solutions biased toward the competitive consumer electronics market(1).
A dual QPSK soft-demapper for ECMA-368 exploiting time-domain spreading and guard interval diversity
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When considering the relative fast processing speed and low power requirements for Wireless Personal Area Networks (WPAN) and Wireless Universal Serial Bus (USB) consumer based products, then the efficiency and cost effectiveness of these products become paramount. This paper presents an improved soft-output QPSK demapper suitable for the products above that not only exploits time diversity and guard carrier diversity, but also merges the demapping and symbol combining functions together to minimize CPU cycles, or memory access dependant upon the chosen implementation architecture. The proposed demapper is presented in the context of Multiband OFDM version of UWB (ECMA-368) as the chosen physical implementation for high-rate Wireless USB.
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A simple and practical technique for assessing the risks, that is, the potential for error, and consequent loss, in software system development, acquired during a requirements engineering phase is described. The technique uses a goal-based requirements analysis as a framework to identify and rate a set of key issues in order to arrive at estimates of the feasibility and adequacy of the requirements. The technique is illustrated and how it has been applied to a real systems development project is shown. How problems in this project could have been identified earlier is shown, thereby avoiding costly additional work and unhappy users.
Resumo:
This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.