Low complexity Bit allocation algorithms for AAC encoding

We have developed two reduced complexity bit-allocation algorithms for MP3/AAC based audio encoding, which can be useful at low bit-rates. One algorithm derives optimum bit-allocation using constrained optimization of weighted noise-to-mask ratio and the second algorithm uses decoupled iterations for distortion control and rate control, with convergence criteria. MUSHRA based evaluation indicated that the new algorithm would be comparable to AAC but requiring only about 1/10 th the complexity.

A Coalition game model for spectrum pooling in wireless data access networks

We consider a setting in which several operators offer downlink wireless data access services in a certain geographical region. Each operator deploys several base stations or access points, and registers some subscribers. In such a situation, if operators pool their infrastructure, and permit the possibility of subscribers being served by any of the cooperating operators, then there can be overall better user satisfaction, and increased operator revenue. We use coalitional game theory to investigate such resource pooling and cooperation between operators.We use utility functions to model user satisfaction, and show that the resulting coalitional game has the property that if all operators cooperate (i.e., form a grand coalition) then there is an operating point that maximizes the sum utility over the operators while providing the operators revenues such that no subset of operators has an incentive to break away from the coalition. We investigate whether such operating points can result in utility unfairness between users of the various operators. We also study other revenue sharing concepts, namely, the nucleolus and the Shapely value. Such investigations throw light on criteria for operators to accept or reject subscribers, based on the service level agreements proposed by them. We also investigate the situation in which only certain subsets of operators may be willing to cooperate.

Micro stepping of Shape Memory Alloy based Poly Phase motor

In literature we find broadly two types of shape memory alloy based motors namely limited rotation motor and unlimited rotation motor. The unlimited rotation type SMA based motor reported in literature uses SMA springs for actuation. An attempt has been made in this paper to develop an unlimited rotation type balanced poly phase motor based on SMA wire in series with a spring in each phase. By isolating SMA actuation and spring action we are able achieve a constant force by the SMA wire through out its range of operation. The Poly phase motor can be used in stepping mode for generating incremental motion and servo mode for generating continuous motion. A method of achieving servo motion by micro stepping is presented. Micro stepping consists of controlling single-phase temperature with a position feedback. The motor has been modeled with a new approach to the SMA wire Hysterysis model. Motor is simulated for different responses and the results are compared with the experimental data.

Java Memory Model aware Software validation

The Java Memory Model (JMM) provides a semantics of Java multithreading for any implementation platform. The JMM is defined in a declarative fashion with an allowed program execution being defined in terms of existence of "commit sequences" (roughly, the order in which actions in the execution are committed). In this work, we develop OpMM, an operational under-approximation of the JMM. The immediate motivation of this work lies in integrating a formal specification of the JMM with software model checkers. We show how our operational memory model description can be integrated into a Java Path Finder (JPF) style model checker for Java programs.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Shape memory alloy based motor

Design and characterization of a new shape memory alloy wire based Poly Phase Motor has been reported in this paper. The motor can be used either in stepping mode or in servo mode of operation. Each phase of the motor consists of an SMA wire with a spring in series. The principle of operation of the poly phase motor is presented. The motor resembles a stepper motor in its functioning though the actuation principles are different and hence has been characterized similar to a stepper motor. The motor can be actuated in either direction with different phase sequencing methods, which are presented in this work. The motor is modelled and simulated and the results of simulations and experiments are presented. The experimental model of the motor is of dimension 150mm square, 20mm thick and uses SMA wire of 0·4mm diameter and 125mm of length in each phase.

Bit Steering In The Minimization Of Control Memory In Microprogrammed Digital-Computers

This correspondence presents an algorithm for microprogram control memory width minimization with the bit steering technique. The necessary and sufficient conditions to detect the steerability of two mutually exclusive sets of microcommands are established. The algorithm encodes the microcommands of the sets with a bit steering common part and also extends the theory to multiple (more than two) sets of microcommands.