Analysis of non-uniform waveguide in MZI and optimization of the power confinement in the waveguide

The technological world has attained a new dimension with the advent of miniaturization and a major breakthrough has evolved in the form of moems, technically more advanced than mems. This breakthrough has paved way for the scientists to research and conceive their innovation. This paper presents a mathematical analysis of the wave propagation along the non-uniform waveguide with refractive index varying along the z axis implemented on the cantilever beam of MZI based moem accelerometer. Secondly the studies on the wave bends with minimum power loss focusing on two main aspects of bend angle and curvature angle is also presented.

A hybrid nine-level inverter for IM drive

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Approximate synthesis formulas for microstrip line with aperture in ground plane

Approximate closed-form expressions for the propagation characteristics of a microstrip line with a symmetrical aperture in its ground plane are reported in this article. Well-known expressions for the characteristic impedance of a regular microstrip line have been modified to incorporate the effect of this aperture. The accuracy of these expressions for various values of substrate thickness, permittivity and line width has been studied in detail by fullwave simulations. This has been further verified by measurements. These expressions are easier to compute and find immense use in the design of broadband filters, tight couplers, power dividers, transformers, delay lines, and matching circuits. A broadband filter with aperture in ground plane is demonstrated in this article. (c) 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.

Chromium Nanowires Grown Inside Lithographically Fabricated U-Trench Templates

Chromium nanowires of diameter 40-120 nm have been grown inside lithographically fabricated U-trench templates on oxidized silicon substrate by RF sputtering deposition technique. Under favourable experimental conditions, very long nanowires can be grown which depends on the trench length and surface homogeneity along the axis. Surface wettability control by the restricted supply of metal vapour is the key for the formation of nanowires. Diameter/depth ratio for the trench template is demonstrated to be crucial for the growth of nanowires.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Microelectromechanical torsional varactors with low parasitic capacitances and high dynamic range

This work focuses on the design of torsional microelectromechanical systems (MEMS) varactors to achieve highdynamic range of capacitances. MEMS varactors fabricated through the polyMUMPS process are characterized at low and high frequencies for their capacitance-voltage characteristics and electrical parasitics. The effect of parasitic capacitances on tuning ratio is studied and an equivalent circuit is developed. Two variants of torsional varactors that help to improve the dynamic range of torsional varactors despite the parasitics are proposed and characterized. A tuning ratio of 1:8, which is the highest reported in literature, has been obtained. We also demonstrate through simulations that much higher tuning ratios can be obtained with the designs proposed. The designs and experimental results presented are relevant to CMOS fabrication processes that use low resistivity substrate. (C) 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). DOI: 10.1117/1.JMM.11.1.013006]

Realization of thermally durable close-packed 2D gold nanoparticle arrays using self-assembly and plasma etching

Realization of thermally and chemically durable, ordered gold nanostructures using bottom-up self-assembly techniques are essential for applications in a wide range of areas including catalysis, energy generation, and sensing. Herein, we describe a modular process for realizing uniform arrays of gold nanoparticles, with interparticle spacings of 2 nm and above, by using RF plasma etching to remove ligands from self-assembled arrays of ligand-coated gold nanoparticles. Both nanoscale imaging and macroscale spectroscopic characterization techniques were used to determine the optimal conditions for plasma etching, namely RF power, operating pressure, duration of treatment, and type of gas. We then studied the effect of nanoparticle size, interparticle spacing, and type of substrate on the thermal durability of plasma-treated and untreated nanoparticle arrays. Plasma-treated arrays showed enhanced chemical and thermal durability, on account of the removal of ligands. To illustrate the application potential of the developed process, robust SERS (surface-enhanced Raman scattering) substrates were formed using plasma-treated arrays of silver-coated gold nanoparticles that had a silicon wafer or photopaper as the underlying support. The measured value of the average SERS enhancement factor (2 x 10(5)) was quantitatively reproducible on both silicon and paper substrates. The silicon substrates gave quantitatively reproducible results even after thermal annealing. The paper-based SERS substrate was also used to swab and detect probe molecules deposited on a solid surface.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Effect of Oxygen Pressure on Structural and Magnetic Properties of YIG Thin Films

The effect of oxygen pressure (P-O2) on the Yttrium Iron Garnet (YIG) thin films were grown on silicon substrate by rf sputtering method was studied. The as-deposited films at 300K were amorphous in nature. The crystallization of these films was achieved by annealing at a temperature of 800 degrees C/1hr in air. The structural, microstructural and magnetic properties were found to be dependent on P-O2.

A novel gas flow sensing application using piezoelectric ZnO thin films deposited on Phynox alloy

We report on the novel flow sensing application of piezoelectric ZnO thin film deposited on Phynox alloy sensing element. Characterization of piezoelectric ZnO films deposited on Phynox (Elgiloy) substrate at different RF powers is discussed. ZnO films deposited at RF power of 100W were found to have fine c-axis orientation, possesses excellent surface morphology with lower rms surface roughness of 1.87 nm and maximum d(31) coefficient value 4.7 pm V-1. The thin cantilever strip of Phynox alloy with ZnO film as a sensing layer for flow sensing has been tested for flow rates ranging from 2 to 18 L min(-1). A detailed theoretical analysis of the experimental set-up showing the relationship between output voltage and force at a particular flow rate has been discussed. The sensitivity of now sensing element is similar to 18 mV/(L min(-1)) and typical response time is of the order of 20 m s. The sensing element is calibrated using in-house developed testing set-up. (C) 2012 Elsevier B.V. All rights reserved.

Unusual Salt-Induced Color Modulation through Aggregation-Induced Emission Switching of a Bis-cationic Phenylenedivinylene-Based pi Hydrogelator

The synthesis, hydrogelation, and aggregation-induced emission switching of the phenylenedivinylene bis-N-octyl pyridinium salt is described. Hydrogelation occurs as a consequence of pi-stacking, van der Waals, and electrostatic interactions that lead to a high gel melting temperature and significant mechanical properties at a very low weight percentage of the gelator. A morphology transition from fiber-to-coil-to-tube was observed depending on the concentration of the gelator. Variation in the added salt type, salt concentrations, or temperature profoundly influenced the order of aggregation of the gelator molecules in aqueous solution. Formation of a novel chromophore assembly in this way leads to an aggregation-induced switch of the emission colors. The emission color switches from sky blue to white to orange depending upon the extent of aggregation through mere addition of external inorganic salts. Remarkably, the salt effect on the assembly of such cationic phenylenedivinylenes in water follow the behavior predicted from the well-known Hofmeister effects. Mechanistic insights for these aggregation processes were obtained through the counterion exchange studies. The aggregation-induced emission switching that leads to a room-temperature white-light emission from a single chromophore in a single solvent (water) is highly promising for optoelectronic applications.

Graphene transistors for CMOS applications: opportunities and challenges

In the last decade, there has been a tremendous interest in Graphene transistors. The greatest advantage for CMOS nanoelectronics applications is the fact that Graphene is compatible with planar CMOS technology and potentially offers excellent short channel properties. Because of the zero bandgap, it will not be possible to turn off the MOSFET efficiently and hence the typical on current to off current ratio (Ion/Ioff) has been less than 10. Several techniques have been proposed to open the bandgap in Graphene. It has been demonstrated, both theoretically and experimentally, that Graphene Nanoribbons (GNR) show a bandgap which is inversely proportional to their width. GNRs with about 20 nm width have bandgaps in the range of 100meV. But it is very difficult to obtain GNRs with well defined edges. An alternate technique to open the band gap is to use bilayer Graphene (BLG), with an asymmetric bias applied in the direction perpendicular to their plane. Another important CMOS metric, the subthreshold slope is also limited by the inability to turn off the transistor. However, these devices could be attractive for RF CMOS applications. But even for analog and RF applications the non-saturating behavior of the drain current can be an issue. Although some studies have reported current saturation, the mechanisms are still not very clear. In this talk we present some of our recent findings, based on simulations and experiments, and propose possible solutions to obtain high on current to off current ratio. A detailed study on high field transport in grapheme transistors, relevant for analog and RF applications will also be presented.

Low-thermal-budget solution processing of thin films of zinc ferrite and other complex oxides

Further miniaturization of magnetic and electronic devices demands thin films of advanced nanomaterials with unique properties. Spinel ferrites have been studied extensively owing to their interesting magnetic and electrical properties coupled with stability against oxidation. Being an important ferrospinel, zinc ferrite has wide applications in the biological (MRI) and electronics (RF-CMOS) arenas. The performance of an oxide like ZnFe2O4 depends on stoichiometry (defect structure), and technological applications require thin films of high density, low porosity and controlled microstructure, which depend on the preparation process. While there are many methods for the synthesis of polycrystalline ZnFe2O4 powder, few methods exist for the deposition of its thin films, where prolonged processing at elevated temperature is not required. We report a novel, microwave-assisted, low temperature (<100°C) deposition process that is conducted in the liquid medium, developed for obtaining high quality, polycrystalline ZnFe2O4 thin films on technologically important substrates like Si(100). An environment-friendly solvent (ethanol) and non-hazardous oxide precursors (β-diketonates of Zn and Fe in 1:2 molar ratio), forming a solution together, is subjected to irradiation in a domestic microwave oven (2.45 GHz) for a few minutes, leading to reactions which result in the deposition of ZnFe2O4 films on Si (100) substrates suspended in the solution. Selected surfactants added to the reactant solution in optimum concentration can be used to control film microstructure. The nominal temperature of the irradiated solution, i.e., film deposition temperature, seldom exceeds 100°C, thus sharply lowering the thermal budget. Surface roughness and uniformity of large area depositions (50x50 mm2) are controlled by tweaking the concentration of the mother solution. Thickness of the films thus grown on Si (100) within 5 min of microwave irradiation can be as high as several microns. The present process, not requiring a vacuum system, carries a very low thermal budget and, together with a proper choice of solvents, is compatible with CMOS integration. This novel solution-based process for depositing highly resistive, adherent, smooth ferrimagnetic films on Si (100) is promising to RF engineers for the fabrication of passive circuit components. It is readily extended to a wide variety of functional oxide films.