Fluctuation quench and hydrophobic collapse of polymers and biopolymers in water-DMSO binary mixture at low DMSO concentration

Binary mixtures have strong influence on activities of polymers and biopolymers even at low cosolvent concentration. Among the several aqueous binary mixtures studied, water-DMSO especially stands out for its unusual behavior at certain specific concentrations of DMSO. In the present work, we study the effect of water-DMSO binary mixture on polymers and biopolymers by taking a simple linear hydrocarbon chain of intermediate length (n = 30) and the protein lysozyme, respectively. We find that at a mole fraction of 0.05 of DMSO (x(DMSO) = 0.05) in aqueous solution, the hydrocarbon chain adopts the collapsed conformation as the most stable and rigid state. In this case of 0.05 mole fraction of DMSO in bulk, the DMSO concentration in the first hydration layer around the polymer is found to be as large as 17%. Formation of such hydrophobic environment around the polymer is the reason for the collapsed state gaining so much stability. Interestingly, similar quench of conformational fluctuation is also observed for the protein investigated. It is observed that in the case of alkane polymer chains, long wavelength fluctuation gets easily quenched, the polymer being purely hydrophobic. However, in case of the protein, quench of fluctuation is prominent only at the hydrophobic surface, and quench of long wavelength fluctuation becomes insignificant for the full protein. As protein contains both hydrophobic and hydrophilic moieties, the extent of quench of conformational fluctuation with respect to that in pure water is almost half for the biopolymer complex (16.83%) than the same for pure hydrophobic polymer chain (32.43%).

Embedded Thin Film Resistors on BCB by Low-Cost PWB Compatible Electroless Plating by Direct Foil Lamination Transfer Processes

Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced system-on-package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties. Realization of embedded resistors on low loss benzocyclobutene (dielectric loss ~0.0008 at > 40 GHz) has been explored in this study. Two approaches, viz, foil transfer and electroless plating have been attempted for deposition of thin film resistors on benzocyclobutene (BCB). Ni-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. This paper reports NiP and NiWP electroless plated embedded resistors on BCB dielectric for the first time in the literature

Recent Advances in Low CTE and High Density System-on-a-Package (SOP) Substrate with Thin Film Component Integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along- - with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation

Geometric representations of graphs in low dimension

We give an efficient randomized algorithm to construct a box representation of any graph G on n vertices in $1.5 (\Delta + 2) \ln n$ dimensions, where $\Delta$ is the maximum degree of G. We also show that $\boxi(G) \le (\Delta + 2) \ln n$ for any graph G. Our bound is tight up to a factor of $\ln n$. We also show that our randomized algorithm can be derandomized to get a polynomial time deterministic algorithm. Though our general upper bound is in terms of maximum degree $\Delta$, we show that for almost all graphs on n vertices, its boxicity is upper bound by $c\cdot(d_{av} + 1) \ln n$ where d_{av} is the average degree and c is a small constant. Also, we show that for any graph G, $\boxi(G) \le \sqrt{8 n d_{av} \ln n}$, which is tight up to a factor of $b \sqrt{\ln n}$ for a constant b.

A Scalable Low Power Issue Queue for Large Instruction Window Processors

Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order superscalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.To address both these issues comprehensively, we propose the Scalable Lowpower Issue Queue (SLIQ). SLIQ augments a pipelined issue queue with direct indexing to mitigate the problem of delayed wakeups while reducing the cycle time. Also, the SLIQ design naturally leads to significant energy savings by reducing both the number of tag broadcasts and comparisons required.A 2 segment SLIQ incurs an average IPC loss of 0.2% over the entire SPEC CPU2000 suite, while achieving a 25.2% reduction in issue latency when compared to a monolithic 128-entry issue queue for an 8-wide superscalar processor. An 8 segment SLIQ improves scalability by reducing the issue latency by 38.3% while incurring an IPC loss of only 2.3%. Further, the 8 segment SLIQ significantly reduces the energy consumption and energy-delay product by 48.3% and 67.4% respectively on average.