943 resultados para Valorization circuit
Resumo:
Design, fabrication and preliminary testing of a flat pump with millimetre thickness are described in this paper. The pump is entirely made of polymer materials barring the magnet and copper coils used for electromagnetic actuation. The fabrication is carried out using widely available microelectronic packaging machinery and techniques. Therefore, the fabrication of the pump is straightforward and inexpensive. Two types of prototypes are designed and built. One consists of copper coils that are etched on an epoxy plate and the other has wound insulated wire of 90 mu m diameter to serve as a coil. The overall size of the first pump is 25 mm x 25 mm x 3.6 mm including the 3.1 mm-thick NdFeB magnet of diameter 12 mm. It consists of a pump chamber of 20 mm x 20 mm x 0.8 mm with copper coils etched from a copper-clad epoxy plate using dry-film lithography and milled using a CNC milling machine, two passive valves and the pump-diaphragm made of Kapton film of 0.089 mm thickness. The second pump has an overall size of 35 mm x 35 mm x 4.4 mm including the magnet and the windings. A breadboard circuit and DC power supply are used to test the pump by applying an alternating square-wave voltage pulse. A water slug in a tube attached to the inlet is used to observe and measure the air-flow induced by the pump against atmospheric pressure. The maximum flow rate was found to be 15 ml/min for a voltage of 2.5 V and a current of 19 mA at 68 Hz.
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Among various MEMS sensors, a rate gyroscope is one of the most complex sensors from the design point of view. The gyro normally consists of a proof mass suspended by an elaborate assembly of beams that allow the system to vibrate in two transverse modes. The structure is normally analysed and designed using commercial FEM packages such as ANSYS or MEMS specific commercial tools such as Coventor or Intellisuite. In either case, the complexity in analysis rises manyfolds when one considers the etch hole topography and the associated fluid flow calculation for damping. In most cases, the FEM analysis becomes prohibitive and one resorts to equivalent electrical circuit simulations using tools like SABER in Coventor. Here, we present a simplified lumped parameter model of the tuning fork gyro and show how easily it can be implemented using a generic tool like SIMULINK. The results obtained are compared with those obtained from more elaborate and intense simulations in Coventor. The comparison shows that lumped parameter SIMULINK model gives equally good results with fractional effort in modelling and computation. Next, the performance of a symmetric and decoupled vibratory gyroscope structure is also evaluated using this approach and a few modifications are made in this design to enhance the sensitivity of the device.
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Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.
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Electro-oxidation of methanol was studied on carbon-supported Pt---Sn/C electrodes in silcotungstic acid (SiWA) at various concentrations. The porous-carbon electrodes employing Pt---Sn/C catalyst have been characterized using chemical analyses, X-ray powder diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) in conjunction with electrochemistry. The presence of Pt---Sn and Pt3Sn alloys along with Pt and SnO2 phases in the catalyst were identified by XRD. XPS analysis showed a lower amount of PtO species in the Pt---Sn/C catalyst with respect to the corresponding Pt/C sample. From the steady-state galvanostatic polarization data on Pt---Sn/C electrodes in SiWA, it is inferred that a one-electron process is the rate determining step. The performance of the electrodes in 0.084 M SiWA was better than in 2.5 M H2SO4 under similar conditions up to load currents of about 100 mA cm−2 indicating the promoting behaviour of the electrolyte. At currents larger than 100 mA cm−2, the performance of the electrodes in 0.084 SiWA was poorer than that in 2.5 M H2SO4 mainly due to the dominance of mass polarization in the former owing to the large size of keggin units associated with the structure of SiWA. This aspect was supported by cyclic voltammetry and ac impedance studies on Pt---Sn/C electrodes. Simulation of the electrochemical impedance response for the oxidation of methanol in SiWA was carried out using the equivalent electrical circuit model.
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This paper proposes a method of sharing power/energy between multiple sources and multiple loads using an integrated magnetic circuit as a junction between sources and sinks. It also presents a particular use of the magnetic circuit as an ac power supply, delivering sinusoidal voltage to load irrespective of the presence of the grid, taking only active power from the grid. The proposed magnetic circuit is a three-energy-port unit, viz.: 1) power/energy from grid; 2) power energy from battery-inverter unit; and 3) power/energy delivery to the load in its particular application as quality ac power supply (QPS). The product provides sinusoidal regulated output voltage, input power-factor correction, electrical isolation between the sources and loads, low battery voltage, and control simplicity. Unlike conventional series-shunt-compensated uninterruptible power supply topologies with low battery voltage, the isolation is provided using a single magnetic circuit that results in a smaller size and lower cost. The circuit operating principles and analysis, as well as simulation and experimental results, are presented for this QPS.
Resumo:
Electro-oxidation of methanol was studied on carbon-supported Pt-Sn/C electrodes in silcotungstic acid (SiWA) at various concentrations. The porous-carbon electrodes employing Pt-Sn/C catalyst have been characterized using chemical analyses, X-ray powder diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) in conjunction with electrochemistry. The presence of Pt-Sn and Pt3Sn alloys along with Pt and SnO2 phases in the catalyst were identified by XRD. XPS analysis showed a lower amount of PtO species in the Pt-Sn/C catalyst with respect to the corresponding Pt/C sample. From the steady-state galvanostatic polarization data on Pt-Sn/C electrodes in SiWA, it is inferred that a one-electron process is the rate determining step. The performance of the electrodes in 0.084 M SiWA was better than in 2.5 M H2SO4 under similar conditions up to load currents of about 100 mA cm-2 indicating the promoting behaviour of the electrolyte. At currents larger than 100 mA cm-2, the performance of the electrodes in 0.084 SiWA was poorer than that in 2.5M H2SO4 mainly due to the dominance of mass polarization in the former owing to the large size of Keggin units associated with the structure of SiWA. This aspect was supported by cyclic voltammetry and ac impedance studies on Pt-Sn/C electrodes. Simulation of the electrochemical impedance response for the oxidation of methanol in SiWA was carried out using the equivalent electrical circuit model.
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This paper presents the analysis and study of voltage collapse at any converter bus in A C-DC systems considering the dynamics of DC system. The problem of voltage instability is acute when HVDC links are connected to weak AC systems, the strength determined by short circuit ratio (SCR) at the converter bus. The converter control strategies are important in determining voltage instability. Small signal analysis is used to identify critical modes and evaluate the effect of AC system strength and control parameters. A sample two-terminal DC system is studied and the results compared with those obtained from static analysis. Also, the results obtained from small signal analysis are validated with nonlinear simulation.
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Anatase titania nanotubes (TNTs) have been synthesized from P25 TiO2 powder by alkali hydrothermal method followed by post annealing. The microstructure analysis by X-ray diffraction (XRD), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) revealed the formation of anatase nanotubes with a diameter of 9-10 nm. These NTs are used to make photo anode in dye-sensitized solar cells (DSSCs). Layer by layer deposition with curing of each layer at 350 C is employed to realize films of desired thickness. The performance of these cells is studied using photovoltaic measurements. Electrochemical impedance spectroscopy (EIS) is used to quantitatively analyze the effect of thickness on the performance of these cells. These studies revealed that the thickness of TiO2 has a pronounced impact on the cell performance and the optimum thickness lies in the range of 10-14 mu m. In comparison to dye solar cells made of P25, TNTs based cells exhibit an improved open circuit voltage and fill factor (FF) due to an increased electron lifetime, as revealed by EIS analysis. (C) 2011 Elsevier B.V. All rights reserved.
Resumo:
Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well
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The internal resistance of a stabilized alpha-nickel hydroxide electrode is found to be lower than that of a beta-nickel hydroxide electrode as shown from studies of the open-circuit potential-time transients at all states-of-charge. Nevertheless, the self-discharge rates of the former is higher. Gasometric studies reveal that the charging efficiency of the alpha-nickel hydroxide electrode is higher than that of the beta-nickel hydroxide electrode.
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A link failure in the path of a virtual circuit in a packet data network will lead to premature disconnection of the circuit by the end-points. A soft failure will result in degraded throughput over the virtual circuit. If these failures can be detected quickly and reliably, then appropriate rerouteing strategies can automatically reroute the virtual circuits that use the failed facility. In this paper, we develop a methodology for analysing and designing failure detection schemes for digital facilities. Based on errored second data, we develop a Markov model for the error and failure behaviour of a T1 trunk. The performance of a detection scheme is characterized by its false alarm probability and the detection delay. Using the Markov model, we analyse the performance of detection schemes that use physical layer or link layer information. The schemes basically rely upon detecting the occurrence of severely errored seconds (SESs). A failure is declared when a counter, that is driven by the occurrence of SESs, reaches a certain threshold.For hard failures, the design problem reduces to a proper choice;of the threshold at which failure is declared, and on the connection reattempt parameters of the virtual circuit end-point session recovery procedures. For soft failures, the performance of a detection scheme depends, in addition, on how long and how frequent the error bursts are in a given failure mode. We also propose and analyse a novel Level 2 detection scheme that relies only upon anomalies observable at Level 2, i.e. CRC failures and idle-fill flag errors. Our results suggest that Level 2 schemes that perform as well as Level 1 schemes are possible.
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Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.
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This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.