Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

Existing and emerging strategies for the synthesis of nanoscale heterostructures

Development of new multifunctional nanostructures relies on the ability to make new materials at the nanoscale with control over size, shape and composition. While this control is extremely important to tune several properties, an alternative strategy is to create active interfaces between two or more nanostructures to form nanoscale heterostructures. In these heterostructures, the interfaces play a key role in stabilizing and enhancing the efficiency of the individual components for various applications. In this article, we discuss synthesis methods of different types of nanoscale heterostructures and the role of interfaces in various applications. We present the current state-of-the-art in designing heterostructures and possible upcoming synthetic strategies with their advantages and disadvantages. We present how such heterostructures are highly efficient for catalytic, photovoltaic and nanoelectronic applications drawing several examples from our own studies and from the literature.

Specification Based Regression Testing Using Explicit State Space Enumeration

This paper presents a method of partial automation of specification based regression testing, which we call ESSE (Explicit State Space Enumeration). The first step in ESSE method is the extraction of a finite state model of the system making use of an already tested version of the system under test (SUT). Thereafter, the finite state model thus obtained is used to compute good test sequences that can be used to regression test subsequent versions of the system. We present two new algorithms for test sequence computation - both based on our finite state model generated by the above method. We also provide the details and results of the experimental evaluation of ESSE method. Comparison with a practically used random-testing algorithm has shown substantial improvements.

An Algorithm for Testing 2-Asummability of Boolean Functions

Simple algorithms have been developed to generate pairs of minterms forming a given 2-sum and thereby to test 2-asummability of switching functions. The 2-asummability testing procedure can be easily implemented on the computer. Since 2-asummability is a necessary and sufficient condition for a switching function of upto eight variables to be linearly separable (LS), it can be used for testing LS switching functions of upto eight variables.