Integrated avalanche diode for 600 v Trench IGBT over-voltage protection

Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (D av) for 600V Trench IGBT over-voltage protection is proposed. The mix-mode transient simulation proves the clamping capability of the D av when the IGBT is experiencing over-voltage stress in unclamped inductive switching (UIS) test. The spread of avalanche energy, which prevents hot-spot formation, through the help of the avalanche diode feeding back a large fraction of the avalanche current to a gate resistance (R G) is also explained. © 2011 IEEE.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Flame interactions in turbulent premixed twin V-flames

Multiple flame-flame interactions in premixed combustion are investigated using direct numerical simulations of twin turbulent V-flames for a range of turbulence intensities and length scales. Interactions are identified using a novel automatic feature extraction (AFE) technique, based on data registration using the dual-tree complex wavelet transform. Information on the time, position, and type of interactions, and their influence on the flame area is extracted using AFE. Characteristic length and time scales for the interactions are identified. The effect of interactions on the flame brush is quantified through a global stretch rate, defined as the sum of flamelet stretch and interaction stretch contributions. The effects of each interaction type are discussed. It is found that the magnitude of the fluctuations in flamelet and interaction stretch are comparable, and a qualitative sensitivity to turbulence length scale is found for one interaction type. Implications for modeling are discussed. © 2013 Copyright Taylor and Francis Group, LLC.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.

Characterization of vertical Mo/diamond Schottky barrier diode from non-ideal I-V and C-V measurements based on MIS model

In this study, we investigated non-ideal characteristics of a diamond Schottky barrier diode with Molybdenum (Mo) Schottky metal fabricated by Microwave Plasma Chemical Vapour Deposition (MPCVD) technique. Extraction from forward bias I-V and reverse bias C- 2-V measurements yields ideality factor of 1.3, Schottky barrier height of 1.872 eV, and on-resistance of 32.63 mö·cm2. The deviation of extracted Schottky barrier height from an ideal value of 2.24 eV (considering Mo workfunction of 4.53 eV) indicates Fermi level pinning at the interface. We attributed such non-ideal behavior to the existence of thin interfacial layer and interface states between metal and diamond which forms Metal-Interfacial layer-Semiconductor (MIS) structure. Oxygen surface treatment during fabrication process might have induced them. From forward bias C-V characteristics, the minimum thickness of the interfacial layer is approximately 0.248 nm. Energy distribution profile of the interface state density is then evaluated from the forward bias I-V characteristics based on the MIS model. The interface state density is found to be uniformly distributed with values around 1013 eV - 1·cm- 2. © 2013 Elsevier B.V.