Effects of reflow process on the reliability of flip chip on flex interconnections using anisotropic conductive adhesives

In this paper, the effects of the solder reflow process on the reliability of anisotropic conductive film (ACF) interconnections for flip chip on flex (FCOF) applications are investigated. Experiments as well as computer modeling methods have been used. In the experiments, it was found that the contact resistance of ACF joints increased after the subsequent reflow process, and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. Nearly 40% of the joints were opened (i.e. lifted away from the pad) after the reflow process with 260 °C peak temperature while no opening was observed when the peak temperature was 210 °C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. It was also found that the ACF joints after the reflow process with 210 °C peak temperature showed a high ability to resist water absorption under steady state 85 °C/85%RH conditions, probably because the curing degree of the ACF was improved during the reflow process. To give a good understanding, a 3D model of an ACF joint structure was built and finite element analysis was used to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process.

Computer modelling of the reliability of flip chips with metal column bumping

Recently, research has been carried out to test a novel bumping method which omits the under bump metallurgy forming process by bonding copper columns directly onto the Al pads of the silicon dies. This bumping method could be adopted to simplify the flip chip manufacturing process, increase the productivity and achieve a higher I/O count. This paper describes an investigation of the solder joint reliability of flip-chips based on this new bumping process. Computer modelling methods are used to predict the shape of solder joints and response of flip chips to thermal cyclic loading. The accumulated plastic strain energy at the comer solder joints is used as the damage indicator. Models with a range of design parameters have been compared for their reliability. The parameters that have been investigated are the copper column height, radius and solder volume. The ranking of the relative importance of these parameters is given. For most of the results presented in the paper, the solder material has been assumed to be the lead-free 96.5Sn3.5Ag alloy but some results for 60Sn40Pb solder joints have also been presented.

Response Surface Modeling and Optimisation for Reliable Electronic Products

The aim of integrating computational mechanics (FEA and CFD) and optimization tools is to speed up dramatically the design process in different application areas concerning reliability in electronic packaging. Design engineers in the electronics manufacturing sector may use these tools to predict key design parameters and configurations (i.e. material properties, product dimensions, design at PCB level. etc) that will guarantee the required product performance. In this paper a modeling strategy coupling computational mechanics techniques with numerical optimization is presented and demonstrated with two problems. The integrated modeling framework is obtained by coupling the multi-physics analysis tool PHYSICA - with the numerical optimization package - Visua/DOC into a fuJly automated design tool for applications in electronic packaging. Thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and life-time under thermal cycling. Also a thermal management design based on multi-physics analysis with coupled thermal-flow-stress modeling is discussed. The Response Surface Modeling Approach in conjunction with Design of Experiments statistical tools is demonstrated and used subsequently by the numerical optimization techniques as a part of this modeling framework. Predictions for reliable electronic assemblies are achieved in an efficient and systematic manner.

Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.

Lifetime assessment of electronic components for high reliability aerospace applications

This paper details a modelling approach for assessing the in-service (field) reliability and thermal fatigue life-time of electronic package interconnects for components used in the assembly of an aerospace system. The Finite Element slice model of a Plastic Ball Grid Array (PBGA) package and suitable energy based damage models for crack length predictions are used in this study. Thermal fatigue damage induced in tin-lead solder joints are investigated by simulating the crack growth process under a set of prescribed field temperature profiles that cover the period of operational life. The overall crack length in the solder joint for all different thermal profiles and number of cycles for each profile is predicted using a superposition technique. The effect of using an underfill is also presented. A procedure for verifying the field lifetime predictions for the electronic package by using reliability assessment under Accelerated Thermal Cycle (ATC) testing is also briefly outlined.

Moisture Effects on the Reliability of Anisotropic Conductive Film Interconnection for Flip Chip on Flex Applications

Anisotropic conductive film (ACF) which consists of an adhesive epoxy matrix and randomly distributed conductive particles are widely used as the connection material for electronic devices with high I/O counts. However, for the semiconductor industry the reliability of the ACF is still a major concern due to a lack of experimental reliability data. This paper reports the investigations into the moisture-induced failures in Flip-Chip-on-Flex interconnections with Anisotropic Conductive Films (ACFs). Both experimental and modeling methods were applied. In the experiments, the contact resistance was used as a quality indicator and was measured continuously during the accelerated tests (autoclave tests). The temperature, relative humidity and the pressure were set at 121°C, 100%RH, and 2atm respectively. The contact resistance of the ACF joints increased during the tests and nearly 25% of the joints were found to be open after 168 hours’ testing time. Visible conduction gaps between the adhesive and substrate pads were observed. Cracks at the adhesive/flex interface were also found. For a better understanding of the experimental results, 3-D Finite Element (FE) models were built and a macro-micro modeling method was used to determine the moisture diffusion and moisture-induced stresses inside the ACF joints. Modeling results are consistent with the findings in the experimental work.

Moisture Effects on the Reliability of Anisotropic Conductive Films

Anisotropic conductive film (ACF) which consists of an adhesive epoxy matrix and randomly distributed conductive particles are widely used as the connection material for electronic devices with high I/O counts. However, for the semiconductor industry the reliability of the ACF is still a major concern due to a lack of experimental reliability data. This paper reports an investigation into the moisture effects on the reliability of ACF interconnections in the flip-chip-on-flex (FCOF) applications. A macro-micro 3D finite element modeling technique was used in order to make the multi-length-scale modeling of the ACF flip chip possible. The purposes of this modeling work was to understand the role that moisture plays in the failure of ACF flip chips, and to look into the influence of physical properties and geometric characteristics, such as the coefficient of the moisture expansion (CME), Young's modulus of the adhesive matrix and the bump height on the reliability of the ACF interconnections in a humid environment. Simulation results suggest that moisture-induced swelling of the adhesive matrix is the major cause of the ACF joint opening. Modeling results are consistent with the findings in the experimental work.

Effects of solder reflow on the reliability of flip-chip on flex interconnections using anisotropic conductive adhesives

This work describes the work of an investigation of the effects of solder reflow process on the reliability of anisotropic conductive film (ACF) interconnection for flip-chip on flex (FCOF) applications. Experiments as well as computer modeling methods have been used. The results show that the contact resistance of ACF interconnections increases after the reflow and the magnitude of the increase is strongly correlated to the peak reflow temperature. In fact, nearly 40 percent of the joints are open when the peak reflow temperature is 260°C, while there is no opening when the peak temperature is 210°C. It is believed that the coefficient of thermal expansion (CTE) mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a three-dimensional (3-D) finite element (FE) model of an ACF joint has been analyzed in order to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process. The stress level at the interface between the particle and its surrounding materials is significant and it is the highest at the interface between the particle and the adhesive matrix.

Decision support systems for eco-friendly electronic products

This paper discusses an optimisation based decision support system and methodology for electronic packaging and product design and development which is capable of addressing in efficient manner specified environmental, reliability and cost requirements. A study which focuses on the design of a flip-chip package is presented. Different alternatives for the design of the flip-chip package are considered based on existing options for the applied underfill and volume of solder material used to form the interconnects. Variations in these design input parameters have simultaneous effect on package aspects such as cost, environmental impact and reliability. A decision system for the design of the flip-chip that uses numerical optimisation approach is used to identify the package optimal specification which satisfies the imposed requirements. The reliability aspect of interest is the fatigue of solder joints under thermal cycling. Transient nonlinear finite element analysis (FEA) is used to simulate the thermal fatigue damage in solder joints subject to thermal cycling. Simulation results are manipulated within design of experiments and response surface modelling framework to provide numerical model for reliability which can be used to quantify the package reliability. Assessment of the environmental impact of the package materials is performed by using so called Toxic Index (TI). In this paper we demonstrate the evaluation of the environmental impact only for underfill and lead-free solder materials. This evaluation is based on the amount of material per flip-chip package. Cost is the dominant factor in contemporary flip-chip packaging industry. In the optimisation based decision support system for the design of the flip-chip package, cost of materials which varies as a result of variations in the design parameters is considered.

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

An analysis of the passenger to cabin crew ratio and exit reliability based on past survivable aviation accidents

A hotly debated issue in the area of aviation safety is the number of cabin crew members required to evacuate an aircraft in the event of an emergency. Most countries regulate the minimum number required for the safe operation of an aircraft, but these rulings are based on little if any scientific evidence. Another issue of concern is the failure rate of exits and slides. This paper examines these issues using the latest version of Aircraft Accident Statistics and Knowledge database AASK V4.0, which contains information from 105 survivable crashes and more than 2,000 survivors, including accounts from 155 cabin crew members.

Reliability study of the electroless Ni–P layer against solder alloy

Copper (Cu) has been widely used in the under bump metallurgy of chip and substrate metallization for chip packaging. However, due to the rapid formation of Cu–Sn intermetallic compound (IMC) at the tin-based solder/Cu interface during solder reaction, the reliability of this type of solder joint is a serious concern. In this work, electroless nickel–phosphorous (Ni–P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials. The deposition was carried out in a commercial acidic sodium hypophosphite bath at 85 °C for different pH values. It was found that for the same deposition time period, higher pH bath composition (mild acidic) yields thicker Ni–P layer with lower phosphorous content. Solder balls having composition 62%Sn–36%Pb–2%Ag were reflowed at 240 °C for 1 to 180 min on three types of electroless Ni–P layers deposited at the pH value of 4, 4.8 and 6, respectively. Thermal stability of the electroless Ni–P barrier layer against the Sn–36%Pb–2%Ag solder reflowed for different time periods was examined by scanning electron microscopy equipped with energy dispersed X-ray. Solder ball shear test was performed in order to find out the relationship between the mechanical strength of solder joints and the characteristics of the electroless Ni–P layer deposited. The layer deposited in the pH 4 acidic bath showed the weak barrier against reflow soldering whereas layer deposited in pH 6 acidic bath showed better barrier against reflow soldering. Mechanical strength of the joints were deteriorated quickly in the layer deposited at pH 4 acidic bath, which was found to be thin and has a high phosphorous content. From the cross-sectional studies and fracture surface analyses, it was found that the appearance of the dark crystalline phosphorous-rich Ni layer weakened the interface and hence lower solder ball shear strength. Ni–Sn IMC formed at the interfaces was found to be more stable at the low phosphorous content (∼14 at.%) layer. Electroless Ni–P deposited at mild acidic bath resulting phosphorous content of around 14 at.% is suggested as the best barrier layer for Sn–36%Pb–2%Ag solder.

Review of methods to predict solder joint reliability under thermo-mechanical cycling

Solder joints are often the cause of failure in electronic devices, failing due to cyclic creep induced ductile fatigue. This paper will review the modelling methods available to predict the lifetime of SnPb and SnAgCu solder joints under thermo-mechanical cycling conditions such as power cycling, accelerated thermal cycling and isothermal testing, the methods do not apply to other damage mechanisms such as vibration or drop-testing. Analytical methods such as recommended by the IPC are covered, which are simple to use but limited in capability. Finite element modelling methods are reviewed, along with the necessary constitutive laws and fatigue laws for solder, these offer the most accurate predictions at the current time. Research on state-of-the-art damage mechanics methods is also presented, although these have not undergone enough experimental validation to be recommended at present

Reliability analysis for power electronics modules

This paper discusses the reliability of power electronics modules. The approach taken combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for the power module structure and most importantly the root cause of a potential failure. The paper details results for two types of failure (i) wire bond fatigue and (ii) substrate delamination. Finite element method modeling techniques have been used to predict the stress distribution within the module structures. A response surface optimisation approach has been employed to enable the optimal design and parameter sensitivity to be determined. The response surface is used by a Monte Carlo method to determine the effects of uncertainty in the design.