Carrier density-dependent transport in poly(3-methylthiophene): from injection-limited to space-charge-limited current

Current-voltage (I-V) and impedance measurements were carried out in doped poly(3-methylthiophene) devices by varying the carrier density. As the carrier concentration reduces the I-V characteristics indicate that the conduction mechanism is limited by metal-polymer interface, as also observed in impedance data. The temperature dependence of I-V in moderately doped samples shows a trap-controlled space-charge-limited conduction (SCLC); whereas in lightly doped devices injection-limited conduction is observed at lower bias and SCLC at higher voltages. The carrier density-dependent quasi-Fermi level adjustment and trap-limited transport could explain this variation in conduction mechanism. Capacitance measurements at lower frequencies and higher bias voltages show a sign change in values due to the significant variations in the relaxation behaviour for lightly and moderately doped samples. The electrical hysteresis increases as carrier density is reduced due to the time scales involved in the de-trapping of carriers.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

Electrical properties of ferroelectric YMnO3 films deposited on n-type Si(111) substrates

YMnO3 thin films were grown on an n-type Si substrate by nebulized spray pyrolysis in the metal-ferroelectric-semiconductor (MFS) configuration. The capacitance-voltage characteristics of the film in the MFS structure exhibit hysteretic behaviour consistent with the polarization charge switching direction, with the memory window decreasing with increase in temperature. The density of the interface states decreases with increasing annealing temperature. Mapping of the silicon energy band gap with the interface states has been carried out. The leakage current, measured in the accumulation region, is lower in well-crystallized thin films and obeys a space-charge limited conduction mechanism. The calculated activation energy from the dc leakage current characteristics of the Arrhenius plot reveals that the activation energy corresponds to oxygen vacancy motion.

Studies on n=2 Aurivillius phases: structure of the series Bi3-xLaxTiNbO9 (0 <= x <= 1)

The crystal structures of the solid solutions of Bi3-xLaxTiNbO9 (0 less than or equal to x less than or equal to 1) have been analyzed by powder X-ray diffraction with supporting evidence from selected area electron diffraction (SAD). The structure of the starting member (x = 0) is verified to be in the orthorhombic space group A2(1) am while the end member (x = 1) is determined to crystallize in the centrosymmetric orthorhombic space group Pmcb. The structure of x = 1 phase is solved by ab initio powder diffraction. The intermediate compositions belong to the space group A2(1) am as confirmed by Rietveld refinements. Rietveld refinements on all the compositions reveal that the La3+ ion is disordered only in the A site and not in the [Bi2O2](2+) layer. The tilt in the Ti/NbO6 octahedra decreases with increasing x. (C) 2003 Elsevier B.V. All rights reserved.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Transient analysis in Al-doped barium strontium titanate thin films grown by pulsed laser deposition

Thin films of (Ba0.5Sr0.5)TiO3 (BST) with different concentrations of Al doping were grown using a pulsed laser deposition technique. dc leakage properties were studied as a function of Al doping level and compared to that of undoped BST films. With an initial Al doping level of 0.1 at. % which substitutes Ti in the lattice site, the films showed a decrease in the leakage current, however, for 1 at. % Al doping level the leakage current was found to be relatively higher. Current time measurements at elevated temperatures on 1 at. % Al doped BST films revealed space-charge transient type characteristics. A complete analysis of the transient characteristics was carried out to identify the charge transport process through variation of applied electric field and ambient temperature. The result revealed a very low mobility process comparable to ionic motion, and was found responsible for the observed feature. Calculation from ionic diffusivity and charge transport revealed a conduction process associated with an activation energy of around 1 eV. The low mobility charge carriers were identified as oxygen vacancies in motion under the application of electric field. Thus a comprehensive understanding of the charge transport process in highly acceptor doped BST was developed and it was conclusive that the excess of oxygen vacancies created by intentional Al doping give rise to space-charge transient type characteristics. © 2001 American Institute of Physics.

Geomagnetic Storms Over India: A Close Look at Historic Space Weather at Mumbai

The swirling colors of aurorae, familiar to many in polar communities, can occasionally be seen at middle latitudes in locations such as southern Canada and central Europe. But in rare instances, aurorae can even be seen in the tropics. On 6 February 1872, news of the sighting of one such aurora was carried by the Times of India newspaper. The aurora occurred on 4 February 1872 and, as noted, was also observed over the Middle East.

An Empirical Evaluation of Novelty-SAPPhIRE Relationship

The research shown in this paper is to check whether a framework for designing: GEMS of SAPPhIRE as req-sol, developed earlier, can support in the designing of novel concepts. This is done by asking the questions: (a) Is there a relationship between the constructs of the framework and novelty? (b) If there is a relationship, what is the degree of this relationship? A hypothesis — an increase in the size and variety of ideas used while designing should enhance the variety of concepts produced, leading to an increase in the novelty of the concept space — is developed to explain the relationship between novelty and the constructs. Eight existing observational studies of designing sessions, each involving an individual designer solving a conceptual design problem by following a think aloud protocol are used for the analysis. The hypothesis is verified empirically using the observational studies. Results also show a strong correlation between novelty and the constructs of the framework; correlation value decreases as the abstraction level of the constructs reduces, signifying the importance of using constructs at higher abstraction levels especially for novelty.

Identifying Robust Plans through Plan Diagram Reduction

Estimates of predicate selectivities by database query optimizers often differ significantly from those actually encountered during query execution, leading to poor plan choices and inflated response times. In this paper, we investigate mitigating this problem by replacing selectivity error-sensitive plan choices with alternative plans that provide robust performance. Our approach is based on the recent observation that even the complex and dense "plan diagrams" associated with industrial-strength optimizers can be efficiently reduced to "anorexic" equivalents featuring only a few plans, without materially impacting query processing quality. Extensive experimentation with a rich set of TPC-H and TPC-DS-based query templates in a variety of database environments indicate that plan diagram reduction typically retains plans that are substantially resistant to selectivity errors on the base relations. However, it can sometimes also be severely counter-productive, with the replacements performing much worse. We address this problem through a generalized mathematical characterization of plan cost behavior over the parameter space, which lends itself to efficient criteria of when it is safe to reduce. Our strategies are fully non-invasive and have been implemented in the Picasso optimizer visualization tool.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.