Influence of voltage and frequency dimming on power losses in hf electronic ballasts for compact fluorescent lamps

Compact fluorescent lamps (CFLs) incorporating electronic ballasts are widely used in lighting. In many cases, the ability to dim the lamp is a requirement. Dimming can be achieved by varying the switching frequency of the inverter or by changing the voltage supplied to the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in Pspice, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. After verification, the model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2011 IEEE.

Electronic and magnetic properties of Ti(2)O(3), Cr(2)O(3), and Fe(2)O(3) calculated by the screened exchange hybrid density functional.

The electronic and magnetic properties of the transition metal sesqui-oxides Cr(2)O(3), Ti(2)O(3), and Fe(2)O(3) have been calculated using the screened exchange (sX) hybrid density functional. This functional is found to give a band structure, bandgap, and magnetic moment in better agreement with experiment than the local density approximation (LDA) or the LDA+U methods. Ti(2)O(3) is found to be a spin-paired insulator with a bandgap of 0.22 eV in the Ti d orbitals. Cr(2)O(3) in its anti-ferromagnetic phase is an intermediate charge transfer Mott-Hubbard insulator with an indirect bandgap of 3.31 eV. Fe(2)O(3), with anti-ferromagnetic order, is found to be a wide bandgap charge transfer semiconductor with a 2.41 eV gap. Interestingly sX outperforms the HSE functional for the bandgaps of these oxides.

Electronic device with self-aligned electrodes fabricated using additive liquid deposition

The invention provides a multilayer electronic device having electrodes, formed on a laterally extending first layer, the lateral position of each of at least two adjacent electrodes being defined by a channel in the first layer. Each channel is adjacent a deposition region, the material which forms each electrode substantially covering the deposition region to form a continuous conductive structure.

FPGA, physics-based modeling of IGBT and pin diode for hardware co-simulation of complex power electronic converters and systems

This paper presents the steps and the challenges for implementing analytical, physics-based models for the insulated gate bipolar transistor (IGBT) and the PIN diode in hardware and more specifically in field programmable gate arrays (FPGAs). The models can be utilised in hardware co-simulation of complex power electronic converters and entire power systems in order to reduce the simulation time without compromising the accuracy of results. Such a co-simulation allows reliable prediction of the system's performance as well as accurate investigation of the power devices' behaviour during operation. Ultimately, this will allow application-specific optimisation of the devices' structure, circuit topologies as well as enhancement of the control and/or protection schemes.

Towards a fast electro-thermo-mechanical IGBT/Diode simulation framework for design of reliable power electronic converters

This paper describes a methodology that enables fast and reasonably accurate prediction of the reliability of power electronic modules featuring IGBTs and p-i-n diodes, by taking into account thermo-mechanical failure mechanisms of the devices and their associated packaging. In brief, the proposed simulation framework performs two main tasks which are tightly linked together: (i) the generation of the power devices' transient thermal response for realistic long load cycles and (ii) the prediction of the power modules' lifetime based on the obtained temperature profiles. In doing so the first task employs compact, physics-based device models, power losses lookup tables and polynomials and combined material-failure and thermal modelling, while the second task uses advanced reliability tests for failure mode and time-to-failure estimation. The proposed technique is intended to be utilised as a design/optimisation tool for reliable power electronic converters, since it allows easy and fast investigation of the effects that changes in circuit topology or devices' characteristics and packaging have on the reliability of the employed power electronic modules. © 2012 IEEE.