Ground penetrating radar signal processing for landmine detection

Ground penetrating radar; landmine; background clutter removal, buried targets detecting

Speed in early visual processing

Vision, Speed, Electroencephalogram, Gamma Band Activity

Text-book of palaeontology /

v. 2 (1902)

Text-book of paleontology / edited by Charles R. Eastman ... adapted from the German of Karl A. von Zittel...

v. 1

Basic components of cortical processing are shared in visual and auditory modality

Magdeburg, Univ., Fak. für Naturwiss., Diss., 2009

Downstream processing of influenza whole-virions for vaccine production

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2009

Estudos sôbre a alimentação mineral do cafeeiro, X: extração de macronutrientes na colheita pelas variedades "Mundo Novo", "Caturra" e "Bourbon Amarelo"

This paper deals with the determination of the content of macronutrients in pulp and beans of three coffee varieties, namely 'Mundo Novo', 'Caturra Amarelo' and 'Bourbon Amarelo'. Samples were collected in plantations located in the three types of soils herein most of S. Paulo, Brazil, coffee is grown, that is, "terra roxa legítima" (Ribeirão Preto), "massapé-salmourão" (Mocóca), and "arenito de Bauru" (Pindorama). The following main conclusions were drawn after statistical analysis of data obtained hereby. There is no statistical difference among the three varieties . Average contents of macronutrients, as per cent of the dry matter, are the following: N P K Ca Mg S bean 1,71 0,10 1,53 0,27 0,15 0,12 pulps 1.78 0,14 3,75 0,41 0,13 0,15 Samples collected in Mocóca ("massapé-salmourão") had lower N and K contents, probably due to lack of availability of these elements in the soil, as suggested by its analysis. Results obtained in this work are in good agreement with data described elsewhere. Out of the total of elements contained in the whole fruit the following proportions are exported as clean coffee: N - 2/3, P and K - 1/2, Ca, Mg and S - 1/3. It is clear therefore that a substantial amount of elements absorbed from the soil remains in the pulp or in the dry hulls which result from processing. From this fact raises the interest of using these residues as fertilizer in the coffee plantations.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software for Explicitly Parallel Memory-Centric Processor Architecture

Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

Ostrich egg-shell cups of Mesopotamia and the ostrich in ancient and modern times / by Berthold Laufer. 9 plates and 10 text-figures.

no.23(1926)

The beginnings of porcelain in China, by Berthold Laufer... with a technical report by H.W. Nichols... Twelve plates and two text-figures...

v.15:no.2(1917)