Topology Optimization of Micromachined Structures with the Manufacturing Constraints of KOH Etching of (110) Silicon

The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

Effect of substrate bias voltage on the structure, electric and dielectric properties of TiO(2) thin films by DC magnetron sputtering

Titanium dioxide (TiO(2)) films have been deposited on glass and p-silicon (1 0 0) substrates by DC magnetron sputtering technique to investigate their structural, electrical and optical properties. The surface composition of the TiO(2) films has been analyzed by X-ray photoelectron spectroscopy. The TiO(2) films formed on unbiased substrates were amorphous. Application of negative bias voltage to the substrate transformed the amorphous TiO(2) into polycrystalline as confirmed by Raman spectroscopic studies. Thin film capacitors with configuration of Al/TiO(2)/p-Si have been fabricated. The leakage current density of unbiased films was 1 x10(-6) A/cm(2) at a gate bias voltage of 1.5 V and it was decreased to 1.41 x 10(-7) A/cm(2) with the increase of substrate bias voltage to -150 V owing to the increase in thickness of interfacial layer of SiO(2). Dielectric properties and AC electrical conductivity of the films were studied at various frequencies for unbiased and biased at -150 V. The capacitance at 1 MHz for unbiased films was 2.42 x 10(-10) F and it increased to 5.8 x 10(-10) F in the films formed at substrate bias voltage of -150 V. Dielectric constant of TiO(2) films were calculated from capacitance-voltage measurements at 1 MHz frequency. The dielectric constant of unbiased films was 6.2 while those formed at -150 V it increased to 19. The optical band gap of the films decreased from 3.50 to 3.42 eV with the increase of substrate bias voltage from 0 to -150 V. (C) 2011 Elsevier B. V. All rights reserved.

Effect of particle size on the giant magnetoresistance of La0.7Ca0.3MnO3

Effect of particle size on the electron transport and magnetic properties of La0.7Ca0.3MnO3 has been investigated. While the ferromagnetic Tc, low field magnetic susceptibility, and insulator‐metal transition are markedly affected by the particle size, the maximum magnetoresistance exhibited by the samples near Tc is not sensitive to the particle size. However, the magnetoresistance at 4.2 K increases with decrease in particle size, suggesting a substantial contribution by the grain boundaries. Preliminary measurements on La0.7Sr0.3MnO3 samples of different particle sizes also corroborate the above conclusions.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

Growth of silicon nanowires by electron beam evaporation using indium catalyst

For the first time silicon nanowires have been grown on indium (In) coated Si (100) substrates using e-beam evaporation at a low substrate temperature of 300 degrees C. Standard spectroscopic and microscopic techniques have been employed for the structural, morphological and compositional properties of as grown Si nanowires. The as grown Si nanowires have randomly oriented with an average length of 600 nm for a deposition time of 15 min. As grown Si nanowires have shown indium nanoparticle (capped) on top of it confirming the Vapor Liquid Solid (VLS) growth mechanism. Transmission Electron Microscope (TEM) measurements have revealed pure and single crystalline nature of Si nanowires. The obtained results have indicated good progress towards finding alternative catalyst to gold for the synthesis of Si nanowires. (C) 2011 Elsevier B.V. All rights reserved.

Combined Raman and infrared investigation of the insulator-to-metal transition in NiS(2-x)Se(x) compounds

Ambient-condition Raman spectra were collected in the strongly correlated NiS(1-x)Se(x) pyrite (0 <= x <= 1.2). Two samples (x = 0 and x = 0.55) were studied as a function of pressure up to 10 GPa, and for the x = 0.55 sample the pressure dependence of the infrared reflectivity was also measured (0-10 GPa). This gave a complete picture of the optical response of that system on approaching the metallic state both by application of pressure and/or by Se alloying, which corresponds to a volume expansion. A peculiar nonmonotonic (V-shaped) volume dependence was found for the quasiparticle spectral weight of both pure and Se-doped compounds. In the x = 0.55 sample the vibrational frequencies of the chalcogen dimer show an anomalous volume dependence on entering the metallic phase. The abrupt softening observed, particularly significant for the Se-Se pair, indicates the relevant role of the softness of the Se-Se bond as previously suggested by theoretical calculations.

Influence of Si-C bond density on the properties of a-Si(1-x)C(x) thin films

Amorphous silicon carbide (a-Si(1-x)C(x)) films were deposited on silicon (100) and quartz substrates by pulsed DC reactive magnetron sputtering of silicon in methane (CH(4))-Argon (Ar) atmosphere. The influence of substrate temperature and target power on the composition, carbon bonding configuration, band gap, refractive index and hardness of a-SiC films has been investigated. Increase in substrate temperature results in slightly decreasing the carbon concentration in the films but favors silicon-carbon (Si-C) bonding. Also lower target powers were favorable towards Si-C bonding. X-ray photoelectron spectroscopy (XPS) results agree with the Fourier Transform Infrared (FTIR), UV-vis spectroscopy results. Increase in substrate temperature resulted in increased hardness of the thin films from 13 to 17 GPa and the corresponding bandgap varied from 2.1 to 1.8 eV. (C) 2011 Elsevier B.V. All rights reserved.

High-Performance Metal-Insulator-Metal Capacitors Using Europium Oxide as Dielectric

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Eu2O3 dielectric for analog and DRAM applications. The influence of different anneal conditions on the electrical characteristics of the fabricated MIM capacitors is studied. FG anneal results in high capacitance density (7 fF/mu m(2)), whereas oxygen anneal results in low quadratic voltage coefficient of capacitance (VCC) (194 ppm/V-2 at 100 kHz), and argon anneal results in low leakage current density (3.2 x 10(-8) A/cm(2) at -1 V). We correlate these electrical results with the surface chemical states of the films through X-ray photoelectron spectroscopy measurements. In particular, FG anneal and argon anneal result in sub-oxides, which modulate the electrical properties.

Bose-Hubbard model in a strong effective magnetic field: Emergence of a chiral Mott insulator ground state

Motivated by experiments on Josephson junction arrays, and cold atoms in an optical lattice in a synthetic magnetic field, we study the ``fully frustrated'' Bose-Hubbard model with half a magnetic flux quantum per plaquette. We obtain the phase diagram of this model on a two-leg ladder at integer filling via the density matrix renormalization group approach, complemented by Monte Carlo simulations on an effective classical XY model. The ground state at intermediate correlations is consistently shown to be a chiral Mott insulator (CMI) with a gap to all excitations and staggered loop currents which spontaneously break time-reversal symmetry. We characterize the CMI state as a vortex supersolid or an indirect exciton condensate, and discuss various experimental implications.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Influence of annealing on oxidation, microstructure and mechanical properties of Ni-49Ti films

Thin films of Ni-49 at.% Ti were deposited by DC magnetron sputtering on silicon substrates at 300 degrees C. The as-deposited amorphous films were annealed at a vacuum of 10(-6) mbar at various temperatures between 300 and 650 degrees C to study the effect of annealing on microstructure and mechanical properties. The as-deposited films showed partial crystallization on annealing at 500 degrees C. At 500 degrees C, a distinct oxidation layer, rich in titanium but depleted in Ni, was seen on the film surface. A gradual increase in thickness and number of layers of various oxide stoichiometries as well as growth of triangular shaped reaction zones were seen with increase in annealing temperature up to 650 degrees C. Nanoindentation studies showed that the film hardness values increase with increase in annealing temperature up to 600 degrees C and subsequently decrease at 650 degrees C. The results were explained on the basis of the change in microstructure as a result of oxidation on annealing.

Physics-Based Band Gap Model for Relaxed and Strained 100] Silicon Nanowires

In this paper, we propose a physics-based simplified analytical model of the energy band gap and electron effective mass in a relaxed and strained rectangular 100] silicon nanowires (SiNWs). Our proposed formulation is based on the effective mass approximation for the nondegenerate two-band model and 4 x 4 Luttinger Hamiltonian for energy dispersion relation of conduction band electrons and the valence band heavy and light holes, respectively. Using this, we demonstrate the effect of the uniaxial strain applied along 100]-direction and a biaxial strain, which is assumed to be decomposed from a hydrostatic deformation along 001] followed by a uniaxial one along the 100]-direction, respectively, on both the band gap and the transport and subband electron effective masses in SiNW. Our analytical model is in good agreement with the extracted data using the extended-Huckel-method-based numerical simulations over a wide range of device dimensions and applied strain.

Synchronous and asynchronous Mott transitions in topological insulator ribbons

We address how the nature of linearly dispersing edge states of two-dimensional (2D) topological insulators evolves with increasing electron-electron correlation engendered by a Hubbard-like on-site repulsion U in finite ribbons of two models of topological band insulators. Using an inhomogeneous cluster slave-rotor mean-field method developed here, we show that electronic correlations drive the topologically nontrivial phase into a Mott insulating phase via two different routes. In a synchronous transition, the entire ribbon attains a Mott insulating state at one critical U that depends weakly on the width of the ribbon. In the second, asynchronous route, Mott localization first occurs on the edge layers at a smaller critical value of electronic interaction, which then propagates into the bulk as U is further increased until all layers of the ribbon become Mott localized. We show that the kind of Mott transition that takes place is determined by certain properties of the linearly dispersing edge states which characterize the topological resilience to Mott localization.

Synthesis and characterization of nano silicon and titanium nitride powders using atmospheric microwave plasma technique

We have demonstrated a simple, scalable and inexpensive method based on microwave plasma for synthesizing 5 to 10 g/h of nanomaterials. Luminescent nano silicon particles were synthesized by homogenous nucleation of silicon vapour produced by the radial injection of silicon tetrachloride vapour and nano titanium nitride was synthesized by using liquid titanium tetrachloride as the precursor. The synthesized nano silicon and titanium nitride powders were characterized by XRD, XPS, TEM, SEM and BET. The characterization techniques indicated that the synthesized powders were indeed crystalline nanomaterials.