FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.

Towards Self-Learning Radio-Based Localization Systems

Location-awareness indoors will be an inseparable feature of mobile services/applications in future wireless networks. Its current ubiquitous availability is still obstructed by technological challenges and privacy issues. We propose an innovative approach towards the concept of indoor positioning with main goal to develop a system that is self-learning and able to adapt to various radio propagation environments. The approach combines estimation of propagation conditions, subsequent appropriate channel modelling and optimisation feedback to the used positioning algorithm. Main advantages of the proposal are decreased system set-up effort, automatic re-calibration and increased precision.

Dual-loop circuits in postoperative atrial macro re-entrant tachycardias

Background Patients late after open-heart surgery may develop dual-loop reentrant atrial arrhythmias, and mapping and catheter ablation remain challenging despite computer-assisted mapping techniques. Objectives The purpose of the study was to demonstrate the prevalence and characteristics of dual-loop reentrant arrhythmias, and to define the optimal mapping and ablation strategy. Methods Fourty consecutive patients (mean age 52+/-12 years) with intra-atrial reentrant tachycardia (IART) after open-heart surgery (with an incision of the right atrial free wall) were studied. Dual-loop IART was defined as the presence of two simultaneous atrial circuits. Following an abrupt tachycardia change during radiofrequency (RF) ablation, electrical disconnection of the targeted reentry isthmus from the remaining circuit was demonstrated by entrainment mapping. Furthermore, the second circuit loop was localized using electroanatomic mapping and/or entrainment mapping. Results Dual-loop IART was demonstrated in 8 patients (20%, 5 patients with congenital heart disease, 3 with acquired heart disease). Dual-loop IART included an isthmus-dependant atrial flutter combined with a reentry related to the atriotomy scar. The diagnosis of dual-loop IART required the comparison of entrainment mapping before and after tachycardiamodification. Overall, 35 patients had successful RF ablation (88%). Success rates were lower in patients with dual-loop IART than in patient without dual-loop IART. Ablation failures in 3 patients with dual-loop IART were related to the inability to properly transect the second tachycardia isthmus in the right atrial free wall. Conclusions Dual-loop IART is relatively common after heart surgery involving a right atriotomy. Abrupt tachycardia change and specific entrainment mapping maneuvers demonstrate these circuits. Electroanatomic mapping appears to be important to assist catheter ablation of periatriotomy circuits.