918 resultados para Hardware and Architecture
Resumo:
The activated sludge process - the main biological technology usually applied to wastewater treatment plants (WWTP) - directly depends on live beings (microorganisms), and therefore on unforeseen changes produced by them. It could be possible to get a good plant operation if the supervisory control system is able to react to the changes and deviations in the system and can take the necessary actions to restore the system’s performance. These decisions are often based both on physical, chemical, microbiological principles (suitable to be modelled by conventional control algorithms) and on some knowledge (suitable to be modelled by knowledge-based systems). But one of the key problems in knowledge-based control systems design is the development of an architecture able to manage efficiently the different elements of the process (integrated architecture), to learn from previous cases (spec@c experimental knowledge) and to acquire the domain knowledge (general expert knowledge). These problems increase when the process belongs to an ill-structured domain and is composed of several complex operational units. Therefore, an integrated and distributed AI architecture seems to be a good choice. This paper proposes an integrated and distributed supervisory multi-level architecture for the supervision of WWTP, that overcomes some of the main troubles of classical control techniques and those of knowledge-based systems applied to real world systems
Resumo:
The introduction of my contribution contains a brief information on the Faculty of Architecture of the Slovak University of Technology in Bratislava (FA STU) and the architectural research performed at this institution. Schemes and priorities of our research in architecture have changed several times since the very beginning in early 50’s. The most significant change occurred after “the velvet revolution” in 1989. Since 1990 there have been several sources to support research at universities. The significant part of my contribution is rooted in my own research experience since the time I had joined FA STU in 1975 as a young architect and researcher. The period of the 80’s is characterized by the first unintentional attempts to do “research by design” and my “scientific” achievements as by-products of my design work. Some of them resulted in the following issues: conception of mezzo-space, theory of the complex perception of architectural space and definition of basic principles of ecologically conscious architecture. Nowadays I continue my research by design within the application of so called solar envelope in urban scale with my students.
Resumo:
The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.