Direct temperature mapping of nanoscale plasmonic devices.

Side by side with the great advantages of plasmonics in nanoscale light confinement, the inevitable ohmic loss results in significant joule heating in plasmonic devices. Therefore, understanding optical-induced heat generation and heat transport in integrated on-chip plasmonic devices is of major importance. Specifically, there is a need for in situ visualization of electromagnetic induced thermal energy distribution with high spatial resolution. This paper studies the heat distribution in silicon plasmonic nanotips. Light is coupled to the plasmonic nanotips from a silicon nanowaveguide that is integrated with the tip on chip. Heat is generated by light absorption in the metal surrounding the silicon nanotip. The steady-state thermal distribution is studied numerically and measured experimentally using the approach of scanning thermal microscopy. It is shown that following the nanoscale heat generation by a 10 mW light source within a silicon photonic waveguide the temperature in the region of the nanotip is increased by ∼ 15 °C compared with the ambient temperature. Furthermore, we also perform a numerical study of the dynamics of the heat transport. Given the nanoscale dimensions of the structure, significant heating is expected to occur within the time frame of picoseconds. The capability of measuring temperature distribution of plasmonic structures at the nanoscale is shown to be a powerful tool and may be used in future applications related to thermal plasmonic applications such as control heating of liquids, thermal photovoltaic, nanochemistry, medicine, heat-assisted magnetic memories, and nanolithography.

Subwavelength plasmonics for graded-index optics on a chip.

Planar plasmonic devices are becoming attractive for myriad applications, owing to their potential compatibility with standard microelectronics technology and the capability for densely integrating a large variety of plasmonic devices on a chip. Mitigating the challenges of using plasmonics in on-chip configurations requires precise control over the properties of plasmonic modes, in particular their shape and size. Here we achieve this goal by demonstrating a planar plasmonic graded-index lens focusing surface plasmons propagating along the device. The plasmonic mode is manipulated by carving subwavelength features into a dielectric layer positioned on top of a uniform metal film, allowing the local effective index of the plasmonic mode to be controlled using a single binary lithographic step. Focusing and divergence of surface plasmons is demonstrated experimentally. The demonstrated approach can be used for manipulating the propagation of surface plasmons, e.g., for beam steering, splitting, cloaking, mode matching, and beam shaping applications.

High resolution direct measurement of temperature distribution in silicon nanophotonics devices.

Following the miniaturization of photonic devices and the increase in data rates, the issues of self heating and heat removal in active nanophotonic devices should be considered and studied in more details. In this paper we use the approach of Scanning Thermal Microscopy (SThM) to obtain an image of the temperature field of a silicon micro ring resonator with sub-micron spatial resolution. The temperature rise in the device is a result of self heating which is caused by free carrier absorption in the doped silicon. The temperature is measured locally and directly using a temperature sensitive AFM probe. We show that this local temperature measurement is feasible in the photonic device despite the perturbation that is introduced by the probe. Using the above method we observed a significant self heating of about 10 degrees within the device.

Nanoscale temperature mapping of photonic and plasmonic devices

We experimentally demonstrate nanoscale thermal mapping of light induced heat in photonic and plasmonic devices using a thermocouple AFM tip. Numerical simulations results and nanoscale temperature measurements are presented and discussed. © OSA 2013.

Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap, which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices. © 2013 American Chemical Society.

Determination of PAH, PCB, and OCP in water from the Three Gorges Reservoir accumulated by semipermeable membrane devices (SPMD)

Bioavailable water concentrations of polycyclic aromatic hydrocarbons (PAH), polychlorinated biphenyls (PCB) and organochlorine pesticides (OCP) were measured in the water column from Three Gorges Reservoir (TGR) collected in May 2008 using semipermeable membrane devices (SPMDs). The sampling sites spanned the whole reservoir from the upstream Chongqing to the great dam covering more than 600 km long distance with water flow velocities ranging from <0.05 to 1.5 m s(-1). This is the first experience of SPMD application in the biggest reservoir in the world. The results of water sampling rates based on performance reference compounds (PRC) were tested to be significantly correlated with water flow velocities in the big river. Results of back-calculated aqueous concentrations based on PRC showed obvious regional variations of PAH, PCB and OCP levels in the reservoir. Total PAH ranged from 13.8 to 97.2 ng L-1, with the higher concentrations occurring in the region of upstream and near the dam. Phenanthrene, fluoranthene, pyrene and chrysene were the predominant PAH compounds in TGR water. Total PCB ranged from 0.08 to 0.51 ng L-1, with the highest one occurring in the region near the dam. PCB 28, 52, 101, 138, 153, 180, 118 were the most abundant PCB congeners in the water. The total OCP ranged from 2.33 to 3.60 ng L-1 and the levels showed homogenous distribution in the whole reservoir. HCH, DDT and HCB, PeCB were the major compounds of OCP fingerprints. Based on water quality criteria, the TGR water could be designated as being polluted by HCB and PAH. Data on PAH, PCB and OCP concentrations found in this survey can be used as reference levels for future POP monitoring programmes in TGR. (C) 2009 Elsevier Ltd. All rights reserved.

Optical investigations of the effect of solvent and thermal annealing on the optoelectronic properties of Poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) films

Poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is one of the most promising conducting polymers that can be used as transparent electrode or as buffer layer for organic electronic devices. However, when used as an electrode, its conductivity has to be optimized either by the addition of solvents or by post-deposition processing. In this work, we investigate the effect of the addition of the polar solvent dimethylsulfoxide (DMSO) to an aqueous PEDOT:PSS solution on its optical and electrical properties by the implementation of the Drude model for the analysis of the measured pseudo-dielectric function by Spectroscopic Ellipsometry from the near infrared to the visible-far ultraviolet spectral range. The results show that the addition of DMSO increases significantly the film conductivity, which reaches a maximum value at an optimum DMSO concentration as it has confirmed by experimentally measured conductivity values. The post-deposition thermal annealing has been found to have a smaller effect on the film conductivity. © 2013 Elsevier B.V.

Assembly and inspection of liquid crystal on silicon devices

Liquid crystal on silicon (LCOS) is one of the most exciting technologies, combining the optical modulation characteristics of liquid crystals with the power and compactness of a silicon backplane. The objective of our work is to improve cell assembly and inspection methods by introducing new equipment for automated assembly and by using an optical inspection microscope. A Suss-MicroTec Universal device bonder is used for precision assembly and device packaging and an Olympus BX51 high resolution microscope is employed for device inspection. © 2009 Optical Society of America.

Crosstalk reduction in holographic wavelength selective switches based on phase-only LCOS devices

A method to reduce crosstalk is proposed for holographic wavelength selective switches (WSSs) using a customized merit function. A reduction in crosstalk >8 dB is measured when multicasting with a phase-only LCOS device. © OSA 2014.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.

High performance transistors based on the controlled growth of triisopropylsilylethynyl-pentacene crystals via non-isotropic solvent evaporation

Triisopropylsilylethynyl-pentacene (TIPS-PEN) has proven to be one of the most promising small molecules in the field of molecular electronics, due to its unique features in terms of stability, performance and ease of processing. Among a wide variety of well-established techniques for the deposition of TIPS-PEN, blade-metered methods have recently gained great interest towards the formation of uniform crystalline films over a large area. Following this rationale, we herein designed a versatile approach based on blade-coating, which overcomes the problem of anisotropic crystal formation by manipulating the solvent evaporation behaviour, in a way that brings about a preferential degree of crystal orientation. The applicability of this method was evaluated by fabricating field-effect transistors on glass as well as on silicon dioxide/silicon (SiO2/Si) substrates. Interestingly, in an attempt to improve the rheological and wetting behaviour of the liquid films on the SiO2/Si substrates, we introduced a polymeric interlayer of polystyrene (PS) or polymethylmethacrylate (PMMA) which concurrently acts as passivation and crystallization assisting layer. In this case, the synergistic effects of the highly-ordered crystalline structure and the oxide surface modification were thoroughly investigated. The overall performance of the fabricated devices revealed excellent electrical characteristics, with high saturation mobilities up to 0.72 cm2 V-1 s-1 (on glass with polymeric dielectric), on/off current ratio >104 and low threshold voltage values (<-5 V). This journal is © the Partner Organisations 2014.

Effect of surface treatment of GaN based light emitting diode wafers on the leakage current of light emitting diode devices

To form low-resistance Ohmic contact to p-type GaN, InGaN/GaN multiple quantum well light emitting diode wafers are treated with boiled aqua regia prior to Ni/Au (5 nm/5 nm) film deposition. The surface morphology of wafers and the current-voltage characteristics of fabricated light emitting diode devices are investigated. It is shown that surface treatment with boiled aqua regia could effectively remove oxide from the surface of the p-GaN layer, and reveal defect-pits whose density is almost the same as the screw dislocation density estimated by x-ray rocking curve measurement. It suggests that the metal atoms of the Ni/Au transparent electrode of light emitting diode devices may diffuse into the p-GaN layer along threading dislocation lines and form additional leakage current channels. Therefore, the surface treatment time with boiled aqua regia should not be too long so as to avoid the increase of threading dislocation-induced leakage current and the degradation of electrical properties of light emitting diodes

Analysis of lateral current spreading in solar cell devices by spatially-resolved electroluminescence

Spatially-resolved electroluminescence (EL) images from solar cells contain information of local current distribution. By theoretical analysis of the EL intensity distribution, the current density distribution under a certain current bias and the sheet resistance can be obtained quantitatively. Two-dimensional numerical simulation of the current density distribution is employed to a GaInP cell, which agrees very well with the experimental results. A reciprocity theorem for current spreading is found and used to interpret the EL images from the viewpoint of current extraction. The optimization of front electrodes is discussed based on the results. (C) 2010 American Institute of Physics. [doi:10.1063/1.3431390]

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.