Allosteric Communication in Cysteinyl tRNA Synthetase A NETWORK OF DIRECT AND INDIRECT READOUT

Protein structure networks are constructed for the identification of long-range signaling pathways in cysteinyl tRNA synthetase (CysRS). Molecular dynamics simulation trajectory of CysRS-ligand complexes were used to determine conformational ensembles in order to gain insight into the allosteric signaling paths. Communication paths between the anticodon binding region and the aminoacylation region have been identified. Extensive interaction between the helix bundle domain and the anticodon binding domain, resulting in structural rigidity in the presence of tRNA, has been detected. Based on the predicted model, six residues along the communication paths have been examined by mutations (single and double) and shown to mediate a coordinated coupling between anticodon recognition and activation of amino acid at the active site. This study on CysRS clearly shows that specific key residues, which are involved in communication between distal sites in allosteric proteins but may be elusive in direct structure analysis, can be identified from dynamics of protein structure networks.

Fracture analysis of concrete using singular fractal functions with lattice beam network and confirmation with acoustic emission study

In the present study singular fractal functions (SFF) were used to generate stress-strain plots for quasibrittle material like concrete and cement mortar and subsequently stress-strain plot of cement mortar obtained using SFF was used for modeling fracture process in concrete. The fracture surface of concrete is rough and irregular. The fracture surface of concrete is affected by the concrete's microstructure that is influenced by water cement ratio, grade of cement and type of aggregate 11-41. Also the macrostructural properties such as the size and shape of the specimen, the initial notch length and the rate of loading contribute to the shape of the fracture surface of concrete. It is known that concrete is a heterogeneous and quasi-brittle material containing micro-defects and its mechanical properties strongly relate to the presence of micro-pores and micro-cracks in concrete 11-41. The damage in concrete is believed to be mainly due to initiation and development of micro-defects with irregularity and fractal characteristics. However, repeated observations at various magnifications also reveal a variety of additional structures that fall between the `micro' and the `macro' and have not yet been described satisfactorily in a systematic manner [1-11,15-17]. The concept of singular fractal functions by Mosolov was used to generate stress-strain plot of cement concrete, cement mortar and subsequently the stress-strain plot of cement mortar was used in two-dimensional lattice model [28]. A two-dimensional lattice model was used to study concrete fracture by considering softening of matrix (cement mortar). The results obtained from simulations with lattice model show softening behavior of concrete and fairly agrees with the experimental results. The number of fractured elements are compared with the acoustic emission (AE) hits. The trend in the cumulative fractured beam elements in the lattice fracture simulation reasonably reflected the trend in the recorded AE measurements. In other words, the pattern in which AE hits were distributed around the notch has the same trend as that of the fractured elements around the notch which is in support of lattice model. (C) 2011 Elsevier Ltd. All rights reserved.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

Network governance at local — A comparative approach

Factors influencing the effectiveness of democratic institutions and to that effect processes involved at the local governance level have been the interest in the literature, given the presence of various advocacies and networks that are context-specific. This paper is motivated to understand the adaptability issues related to governance given these complexities through a comparative analysis of diversified regions. We adopted a two-stage clustering along with regression methodology for this purpose. The results show that the formation of advocacies and networks depends on the context and institutional framework. The paper concludes by exploring different strategies and dynamics involved in network governance and insists on the importance of governing the networks for structural reformation through regional policy making.

Degrees of freedom of relay aided MIMO X network with orthogonal components

We consider the one-way relay aided MIMO X fading Channel where there are two transmitters and two receivers along with a relay with M antennas at every node. Every transmitter wants to transmit messages to every other receiver. The relay broadcasts to the receivers along a noisy link which is independent of the transmitters channel. In literature, this is referred to as a relay with orthogonal components. We derive an upper bound on the degrees of freedom of such a network. Next we show that the upper bound is tight by proposing an achievability scheme based on signal space alignment for the same for M = 2 antennas at every node.

On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components

Video streaming applications have hitherto been supported by single server systems. A major drawback of such a solution is that it increases the server load. The server restricts the number of clients that can be simultaneously supported due to limitation in bandwidth. The constraints of a single server system can be overcome in video streaming if we exploit the endless resources available in a distributed and networked system. We explore a P2P system for streaming video applications. In this paper we build a P2P streaming video (SVP2P) service in which multiple peers co-operate to serve video segments for new requests, thereby reducing server load and bandwidth used. Our simulation shows the playback latency using SVP2P is roughly 1/4th of the latency incurred when the server directly streams the video. Bandwidth consumed for control messages (overhead) is as low as 1.5% of the total data transfered. The most important observation is that the capacity of the SVP2P grows dynamically.

A generalized network alignment for three-source three-destination multiple unicast networks with delays

The concept of interference alignment when extended to three-source three-destination instantaneous multiple unicast network for the case where, each source-destination pair has a min-cut of 1 and zero-interference conditions are not satisfied, is known to achieve a rate of half for every source-destination pair under certain conditions [6]. This was called network alignment. We generalize this concept of network alignment to three-source three-destination multiple unicast (3S-3D-MU) networks with delays, without making use of memory at the intermediate nodes (i.e., nodes other than the sources and destinations) and using time varying Local Encoding Kernels (LEKs). This achieves half the rate corresponding to the individual source-destination min-cut for some classes of 3S-3D-MU network with delays which do not satisfy the zero-interference conditions.

Stability of control systems with time delay

To find the approximate stability limit on the forward gain in control systems with small time delay, this note suggests approximating the exponential in the characteristic equation by the first few terms of its series and using the Routh–Hurwitz criterion. This approximation avoids all the time-consuming graphical work and gives a somewhat pessimistic maximum bound for the gain constant.

Queuing Network Models for Aircraft Availability and Spares Management

Interactions of major activities involved in airfleet operations, maintenance, and logistics are investigated in the framework of closed queuing networks with finite number of customers. The system is viewed at three levels, namely: operations at the flying-base, maintenance at the repair-depot, and logistics for subsystems and their interactions in achieving the system objectives. Several performance measures (eg, availability of aircraft at the flying-base, mean number of aircraft on ground at different stages of repair, use of repair facilities, and mean time an aircraft spends in various stages of repair) can easily be computed in this framework. At the subsystem level the quantities of interest are the unavailability (probability of stockout) of a spare and the duration of its unavailability. The repair-depot capability is affected by the unavailability of a spare which in turn, adversely affects the availability of aircraft at the flying-base level. Examples illustrate the utility of the proposed models.

Time delay to firing of a triggered vacuum gap with barium titanate in trigger gap

The time delay to the firing of a triggered vacuum gap (t.v.g.) containing barium titanate in the trigger gap is investigated as a function of the main gap voltage, main gap length, trigger pulse duration, trigger current and trigger voltage. The time delay decreases steadily with increasing trigger current and trigger voltage until it reaches saturation. The effect of varying the main gap length and voltage on the time delay is not strong. Before `conditioning�¿ the t.v.g. two groups of time delays, long (>100�¿s) and short (<10�¿s), are simultaneously observed when a large number of trials are conducted. After conditioning, only the group of short time delays are present. This is attributed to the marked reduction of the resistance of the trigger gap across the surface of the solid dielectric resulting directly from the conditioning effect.

Modified McMurray Inverter with Pulse Forming Network Commutation Circuits

The modified McMurray Inverter with Pulse Forming Network (PFN) has been explained. The current and voltage waveshapes of the PFN commutation ci rcuit have been compared with conventional L-commutation circuit. The design method of PFN has been explained. Advantages of this type of commutation have been discussed. Experimental results are given.

Performance modeling and architecture exploration of network processors

This paper proposes a Petri net model for a commercial network processor (Intel iXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, network address translation, and IP security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.

Network pricing for QoS: A 'Regulation' approach

V. S. Borkar’s work was supported in part by grant number III.5(157)/99-ET from the Department of Science and Technology, Government of India. D. Manjunath’s work was supported in part by grant number 1(1)/2004-E-Infra from the Ministry of Information Technology, Government of India.

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.