MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Characterization of phase transformation behaviour and microstructural development of electroless Ni-B coating

Phase transformation behaviour of amorphous electroless Ni-B coating with a targeted composition of Ni-6wt% B is characterized in conjunction with microstructural development and hardness. Microscopic observations of the as-deposited coating display a novel microstructure which is already phase separated at multiple length scales. Spherical colonies of similar to 5 mu m consist of 2-3 mu m nodular regions which are surrounded by similar to 2-3 mu m region that contains fine bands ranging from 10 to 70 nm in width. The appearance of three crystalline phases in this binary system at different stages of heat treatment and the concomitant variation in hardness are shown to arise from nanoscale fluctuations in the as-deposited boron content from 4 to 8 wt%. High temperature annealing reveals continuous crystallization up to 430 degrees C, overlapping with the domain of B loss due to diffusion into the substrate. The implications of such a microstructure for optimal heat treatment procedures are discussed. (C) 2011 Elsevier B.V. All rights reserved.