Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

Nepfix: on-demand cloud elastic simulation of networks of evolutionary processors

Una Red de Procesadores Evolutivos o NEP (por sus siglas en ingles), es un modelo computacional inspirado por el modelo evolutivo de las celulas, específicamente por las reglas de multiplicación de las mismas. Esta inspiración hace que el modelo sea una abstracción sintactica de la manipulation de information de las celulas. En particu¬lar, una NEP define una maquina de cómputo teorica capaz de resolver problemas NP completos de manera eficiente en tóerminos de tiempo. En la praóctica, se espera que las NEP simuladas en móaquinas computacionales convencionales puedan resolver prob¬lemas reales complejos (que requieran ser altamente escalables) a cambio de una alta complejidad espacial. En el modelo NEP, las cóelulas estóan representadas por palabras que codifican sus secuencias de ADN. Informalmente, en cualquier momento de cómputo del sistema, su estado evolutivo se describe como un coleccion de palabras, donde cada una de ellas representa una celula. Estos momentos fijos de evolucion se denominan configuraciones. De manera similar al modelo biologico, las palabras (celulas) mutan y se dividen en base a bio-operaciones sencillas, pero solo aquellas palabras aptas (como ocurre de forma parecida en proceso de selection natural) seran conservadas para la siguiente configuracióon. Una NEP como herramienta de computation, define una arquitectura paralela y distribuida de procesamiento simbolico, en otras palabras, una red de procesadores de lenguajes. Desde el momento en que el modelo fue propuesto a la comunidad científica en el año 2001, múltiples variantes se han desarrollado y sus propiedades respecto a la completitud computacional, eficiencia y universalidad han sido ampliamente estudiadas y demostradas. En la actualidad, por tanto, podemos considerar que el modelo teórico NEP se encuentra en el estadio de la madurez. La motivación principal de este Proyecto de Fin de Grado, es proponer una aproxi-mación práctica que permita dar un salto del modelo teórico NEP a una implantación real que permita su ejecucion en plataformas computacionales de alto rendimiento, con el fin de solucionar problemas complejos que demanda la sociedad actual. Hasta el momento, las herramientas desarrolladas para la simulation del modelo NEP, si bien correctas y con resultados satisfactorios, normalmente estón atadas a su entorno de ejecucion, ya sea el uso de hardware específico o implementaciones particulares de un problema. En este contexto, el propósito fundamental de este trabajo es el desarrollo de Nepfix, una herramienta generica y extensible para la ejecucion de cualquier algo¬ritmo de un modelo NEP (o alguna de sus variantes), ya sea de forma local, como una aplicación tradicional, o distribuida utilizando los servicios de la nube. Nepfix es una aplicacion software desarrollada durante 7 meses y que actualmente se encuentra en su segunda iteration, una vez abandonada la fase de prototipo. Nepfix ha sido disenada como una aplicacion modular escrita en Java 8 y autocontenida, es decir, no requiere de un entorno de ejecucion específico (cualquier maquina virtual de Java es un contenedor vólido). Nepfix contiene dos componentes o móodulos. El primer móodulo corresponde a la ejecución de una NEP y es por lo tanto, el simulador. Para su desarrollo, se ha tenido en cuenta el estado actual del modelo, es decir, las definiciones de los procesadores y filtros mas comunes que conforman la familia del modelo NEP. Adicionalmente, este componente ofrece flexibilidad en la ejecucion, pudiendo ampliar las capacidades del simulador sin modificar Nepfix, usando para ello un lenguaje de scripting. Dentro del desarrollo de este componente, tambióen se ha definido un estóandar de representacióon del modelo NEP basado en el formato JSON y se propone una forma de representation y codificación de las palabras, necesaria para la comunicación entre servidores. Adicional-mente, una característica importante de este componente, es que se puede considerar una aplicacion aislada y por tanto, la estrategia de distribution y ejecución son total-mente independientes. El segundo moódulo, corresponde a la distribucióon de Nepfix en la nube. Este de-sarrollo es el resultado de un proceso de i+D, que tiene una componente científica considerable. Vale la pena resaltar el desarrollo de este modulo no solo por los resul-tados prócticos esperados, sino por el proceso de investigation que se se debe abordar con esta nueva perspectiva para la ejecución de sistemas de computación natural. La principal característica de las aplicaciones que se ejecutan en la nube es que son gestionadas por la plataforma y normalmente se encapsulan en un contenedor. En el caso de Nepfix, este contenedor es una aplicacion Spring que utiliza el protocolo HTTP o AMQP para comunicarse con el resto de instancias. Como valor añadido, Nepfix aborda dos perspectivas de implementation distintas (que han sido desarrolladas en dos iteraciones diferentes) del modelo de distribution y ejecucion, que tienen un impacto muy significativo en las capacidades y restricciones del simulador. En concreto, la primera iteration utiliza un modelo de ejecucion asincrono. En esta perspectiva asincrona, los componentes de la red NEP (procesadores y filtros) son considerados como elementos reactivos a la necesidad de procesar una palabra. Esta implementation es una optimization de una topologia comun en el modelo NEP que permite utilizar herramientas de la nube para lograr un escalado transparente (en lo ref¬erente al balance de carga entre procesadores) pero produce efectos no deseados como indeterminacion en el orden de los resultados o imposibilidad de distribuir eficiente-mente redes fuertemente interconectadas. Por otro lado, la segunda iteration corresponde al modelo de ejecucion sincrono. Los elementos de una red NEP siguen un ciclo inicio-computo-sincronizacion hasta que el problema se ha resuelto. Esta perspectiva sincrona representa fielmente al modelo teórico NEP pero el proceso de sincronizacion es costoso y requiere de infraestructura adicional. En concreto, se requiere un servidor de colas de mensajes RabbitMQ. Sin embargo, en esta perspectiva los beneficios para problemas suficientemente grandes superan a los inconvenientes, ya que la distribuciín es inmediata (no hay restricciones), aunque el proceso de escalado no es trivial. En definitiva, el concepto de Nepfix como marco computacional se puede considerar satisfactorio: la tecnología es viable y los primeros resultados confirman que las carac-terísticas que se buscaban originalmente se han conseguido. Muchos frentes quedan abiertos para futuras investigaciones. En este documento se proponen algunas aproxi-maciones a la solucion de los problemas identificados como la recuperacion de errores y la division dinamica de una NEP en diferentes subdominios. Por otra parte, otros prob-lemas, lejos del alcance de este proyecto, quedan abiertos a un futuro desarrollo como por ejemplo, la estandarización de la representación de las palabras y optimizaciones en la ejecucion del modelo síncrono. Finalmente, algunos resultados preliminares de este Proyecto de Fin de Grado han sido presentados recientemente en formato de artículo científico en la "International Work-Conference on Artificial Neural Networks (IWANN)-2015" y publicados en "Ad-vances in Computational Intelligence" volumen 9094 de "Lecture Notes in Computer Science" de Springer International Publishing. Lo anterior, es una confirmation de que este trabajo mas que un Proyecto de Fin de Grado, es solo el inicio de un trabajo que puede tener mayor repercusion en la comunidad científica. Abstract Network of Evolutionary Processors -NEP is a computational model inspired by the evolution of cell populations, which might model some properties of evolving cell communities at the syntactical level. NEP defines theoretical computing devices able to solve NP complete problems in an efficient manner. In this model, cells are represented by words which encode their DNA sequences. Informally, at any moment of time, the evolutionary system is described by a collection of words, where each word represents one cell. Cells belong to species and their community evolves according to mutations and division which are defined by operations on words. Only those cells are accepted as surviving (correct) ones which are represented by a word in a given set of words, called the genotype space of the species. This feature is analogous with the natural process of evolution. Formally, NEP is based on an architecture for parallel and distributed processing, in other words, a network of language processors. Since the date when NEP was pro¬posed, several extensions and variants have appeared engendering a new set of models named Networks of Bio-inspired Processors (NBP). During this time, several works have proved the computational power of NBP. Specifically, their efficiency, universality, and computational completeness have been thoroughly investigated. Therefore, we can say that the NEP model has reached its maturity. The main motivation for this End of Grade project (EOG project in short) is to propose a practical approximation that allows to close the gap between theoretical NEP model and a practical implementation in high performing computational platforms in order to solve some of high the high complexity problems society requires today. Up until now tools developed to simulate NEPs, while correct and successful, are usu¬ally tightly coupled to the execution environment, using specific software frameworks (Hadoop) or direct hardware usage (GPUs). Within this context the main purpose of this work is the development of Nepfix, a generic and extensible tool that aims to execute algorithms based on NEP model and compatible variants in a local way, similar to a traditional application or in a distributed cloud environment. Nepfix as an application was developed during a 7 month cycle and is undergoing its second iteration once the prototype period was abandoned. Nepfix is designed as a modular self-contained application written in Java 8, that is, no additional external dependencies are required and it does not rely on an specific execution environment, any JVM is a valid container. Nepfix is made of two components or modules. The first module corresponds to the NEP execution and therefore simulation. During the development the current state of the theoretical model was used as a reference including most common filters and processors. Additionally extensibility is provided by the use of Python as a scripting language to run custom logic. Along with the simulation a definition language for NEP has been defined based on JSON as well as a mechanisms to represent words and their possible manipulations. NEP simulator is isolated from distribution and as mentioned before different applications that include it as a dependency are possible, the distribution of NEPs is an example of this. The second module corresponds to executing Nepfix in the cloud. The development carried a heavy R&D process since this front was not explored by other research groups until now. It's important to point out that the development of this module is not focused on results at this point in time, instead we focus on feasibility and discovery of this new perspective to execute natural computing systems and NEPs specifically. The main properties of cloud applications is that they are managed by the platform and are encapsulated in a container. For Nepfix a Spring application becomes the container and the HTTP or AMQP protocols are used for communication with the rest of the instances. Different execution perspectives were studied, namely asynchronous and synchronous models were developed for solving different kind of problems using NEPs. Different limitations and restrictions manifest in both models and are explored in detail in the respective chapters. In conclusion we can consider that Nepfix as a computational framework is suc-cessful: Cloud technology is ready for the challenge and the first results reassure that the properties Nepfix project pursued were met. Many investigation branches are left open for future investigations. In this EOG implementation guidelines are proposed for some of them like error recovery or dynamic NEP splitting. On the other hand other interesting problems that were not in the scope of this project were identified during development like word representation standardization or NEP model optimizations. As a confirmation that the results of this work can be useful to the scientific com-munity a preliminary version of this project was published in The International Work- Conference on Artificial Neural Networks (IWANN) in May 2015. Development has not stopped since that point and while Nepfix in it's current state can not be consid¬ered a final product the most relevant ideas, possible problems and solutions that were produced during the seven months development cycle are worthy to be gathered and presented giving a meaning to this EOG work.

A Wireless Charging System Applying Phase-Shift and Amplitude Control to Maximize Efficiency and Extractable Power

Wireless power transfer (WPT) is an emerging technology with an increasing number of potential applications to transfer power from a transmitter to a mobile receiver over a relatively large air gap. However, its widespread application is hampered due to the relatively low efficiency of current Wireless power transfer (WPT) systems. This study presents a concept to maximize the efficiency as well as to increase the amount of extractable power of a WPT system operating in nonresonant operation. The proposed method is based on actively modifying the equivalent secondary-side load impedance by controlling the phase-shift of the active rectifier and its output voltage level. The presented hardware prototype represents a complete wireless charging system, including a dc-dc converter which is used to charge a battery at the output of the system. Experimental results are shown for the proposed concept in comparison to a conventional synchronous rectification approach. The presented optimization method clearly outperforms state-of-the-art solutions in terms of efficiency and extractable power.

Analysis and Design Considerations of an Electric Vehicle Powertrain regarding Energy Efficiency and Magnetic Field Exposure

En esta tesis se analiza el sistema de tracción de un vehículo eléctrico de batería desde el punto de vista de la eficiencia energética y de la exposición a campos magnéticos por parte de los pasajeros (radiación electromagnética). Este estudio incluye tanto el sistema de almacenamiento de energía como la máquina eléctrica, junto con la electrónica de potencia y los sistemas de control asociados a ambos. Los análisis y los resultados presentados en este texto están basados en modelos matemáticos, simulaciones por ordenador y ensayos experimentales a escala de laboratorio. La investigación llevada a cabo durante esta tesis tuvo siempre un marcado enfoque industrial, a pesar de estar desarrollada en un entorno de considerable carácter universitario. Las líneas de investigación acometidas tuvieron como destinatario final al diseñador y al fabricante del vehículo, a pesar de lo cual algunos de los resultados obtenidos son preliminares y/o excesivamente académicos para resultar de interés industrial. En el ámbito de la eficiencia energética, esta tesis estudia sistemas híbridos de almacenamiento de energía basados en una combinación de baterías de litio y supercondensadores. Este tipo de sistemas son analizados desde el punto de vista de la eficiencia mediante modelos matemáticos y simulaciones, cuantificando el impacto de ésta en otros parámetros tales como el envejecimiento de las baterías. Respecto a la máquina eléctrica, el estudio se ha centrado en máquinas síncronas de imanes permanentes. El análisis de la eficiencia considera tanto el diseño de la máquina como la estrategia de control, dejando parcialmente de lado el inversor y la técnica de modulación (que son incluidos en el estudio como fuentes adicionales de pérdidas, pero no como potenciales fuentes de optimización de la eficiencia). En este sentido, tanto la topología del inversor (trifásico, basado en IGBTs) como la técnica de modulación (control de corriente en banda de histéresis) se establecen desde el principio. El segundo aspecto estudiado en esta tesis es la exposición a campos magnéticos por parte de los pasajeros. Este tema se enfoca desde un punto de vista predictivo, y no desde un punto de vista de diagnóstico, puesto que se ha desarrollado una metodología para estimar el campo magnético generado por los dispositivos de potencia de un vehículo eléctrico. Esta metodología ha sido validada mediante ensayos de laboratorio. Otros aspectos importantes de esta contribución, además de la metodología en sí misma, son las consecuencias que se derivan de ella (por ejemplo, recomendaciones de diseño) y la comprensión del problema proporcionada por esta. Las principales contribuciones de esta tesis se listan a continuación: una recopilación de modelos de pérdidas correspondientes a la mayoría de dispositivos de potencia presentes en un vehículo eléctrico de batería, una metodología para analizar el funcionamiento de un sistema híbrido de almacenamiento de energía para aplicaciones de tracción, una explicación de cómo ponderar energéticamente los puntos de operación par-velocidad de un vehículo eléctrico (de utilidad para evaluar el rendimiento de una máquina eléctrica, por ejemplo), una propuesta de incluir un convertidor DC-DC en el sistema de tracción para minimizar las pérdidas globales del accionamiento (a pesar de las nuevas pérdidas introducidas por el propio DC-DC), una breve comparación entre dos tipos distintos de algoritmos de minimización de pérdidas para máquinas síncronas de imanes permanentes, una metodología predictiva para estimar la exposición a campos magnéticos por parte de los pasajeros de un vehículo eléctrico (debida a los equipos de potencia), y finalmente algunas conclusiones y recomendaciones de diseño respecto a dicha exposición a campos magnéticos. ABSTRACT This dissertation analyzes the powertrain of a battery electric vehicle, focusing on energy efficiency and passenger exposure to electromagnetic fields (electromagnetic radiation). This study comprises the energy storage system as well as the electric machine, along with their associated power electronics and control systems. The analysis and conclusions presented in this dissertation are based on mathematical models, computer simulations and laboratory scale tests. The research performed during this thesis was intended to be of industrial nature, despite being developed in a university. In this sense, the work described in this document was carried out thinking of both the designer and the manufacturer of the vehicle. However, some of the results obtained lack industrial readiness, and therefore they remain utterly academic. Regarding energy efficiency, hybrid energy storage systems consisting in lithium batteries, supercapacitors and up to two DC-DC power converters are considered. These kind of systems are analyzed by means of mathematical models and simulations from the energy efficiency point of view, quantifying its impact on other relevant aspects such as battery aging. Concerning the electric machine, permanent magnet synchronous machines are studied in this work. The energy efficiency analysis comprises the machine design and the control strategy, while the inverter and its modulation technique are taken into account but only as sources of further power losses, and not as potential sources for further efficiency optimization. In this sense, both the inverter topology (3-phase IGBT-based inverter) and the switching technique (hysteresis current control) are fixed from the beginning. The second aspect studied in this work is passenger exposure to magnetic fields. This topic is approached from the prediction point of view, rather than from the diagnosis point of view. In other words, a methodology to estimate the magnetic field generated by the power devices of an electric vehicle is proposed and analyzed in this dissertation. This methodology has been validated by laboratory tests. The most important aspects of this contribution, apart from the methodology itself, are the consequences (for instance, design guidelines) and the understanding of the magnetic radiation issue provided by it. The main contributions of this dissertation are listed next: a compilation of loss models for most of the power devices found in a battery electric vehicle powertrain, a simulation-based methodology to analyze hybrid energy storage performance in traction applications, an explanation of how to assign energy-based weights to different operating points in traction drives (useful when assessing electrical machine performance, for instance), a proposal to include one DC-DC converter in electric powertrains to minimize overall power losses in the system (despite the new losses added by the DC-DC), a brief comparison between two kinds of loss-minimization algorithms for permanent magnet synchronous machines in terms of adaptability and energy efficiency, a predictive methodology to estimate passenger magnetic field exposure due to power devices in an electric vehicle, and finally some useful conclusions and design guidelines concerning magnetic field exposure.

REFLEXOS INDIVIDUAIS DO USO PESSOAL E EXCESSIVO DE COMUNICADORES INSTANTÂNEOS NO AMBIENTE DE TRABALHO

A Internet está inserida no cotidiano do indivíduo, e torna-se cada vez mais acessível por meio de diferentes tipos de dispositivos. Com isto, diversos estudos foram realizados com o intuito de avaliar os reflexos do seu uso excessivo na vida pessoal, acadêmica e profissional. Esta dissertação buscou identificar se a perda de concentração e o isolamento social são alguns dos reflexos individuais que o uso pessoal e excessivo de aplicativos de comunicação instantânea podem resultar no ambiente de trabalho. Entre as variáveis selecionadas para avaliar os aspectos do uso excessivo de comunicadores instantâneos tem-se a distração digital, o controle reduzido de impulso, o conforto social e a solidão. Através de uma abordagem de investigação quantitativa, utilizaram-se escalas aplicadas a uma amostra de 283 pessoas. Os dados foram analisados por meio de técnicas estatísticas multivariadas como a Análise Fatorial Exploratória e para auferir a relação entre as variáveis, a Regressão Linear Múltipla. Os resultados deste estudo confirmam que o uso excessivo de comunicadores instantâneos está positivamente relacionado com a perda de concentração, e a variável distração digital exerce uma influência maior do que o controle reduzido de impulso. De acordo com os resultados, não se podem afirmar que a solidão e o conforto social exercem relações com aumento do isolamento social, devido à ausência do relacionamento entre os construtos.

Neuronal coincidence detection by voltage-sensitive electrical synapses

Coincidence detection is important for functions as diverse as Hebbian learning, binaural localization, and visual attention. We show here that extremely precise coincidence detection is a natural consequence of the normal function of rectifying electrical synapses. Such synapses open to bidirectional current flow when presynaptic cells depolarize relative to their postsynaptic targets and remain open until well after completion of presynaptic spikes. When multiple input neurons fire simultaneously, the synaptic currents sum effectively and produce a large excitatory postsynaptic potential. However, when some inputs are delayed relative to the rest, their contributions are reduced because the early excitatory postsynaptic potential retards the opening of additional voltage-sensitive synapses, and the late synaptic currents are shunted by already opened junctions. These mechanisms account for the ability of the lateral giant neurons of crayfish to sum synchronous inputs, but not inputs separated by only 100 μsec. This coincidence detection enables crayfish to produce reflex escape responses only to very abrupt mechanical stimuli. In light of recent evidence that electrical synapses are common in the mammalian central nervous system, the mechanisms of coincidence detection described here may be widely used in many systems.

Cloning and characterization of a plastidal and a mitochondrial isoform of tobacco protoporphyrinogen IX oxidase

Protoporphyrinogen IX oxidase is the last enzyme in the common pathway of heme and chlorophyll synthesis and provides precursor for the mitochondrial and plastidic heme synthesis and the predominant chlorophyll synthesis in plastids. We cloned two different, full-length tobacco cDNA sequences by complementation of the protoporphyrin-IX-accumulating Escherichia coli hemG mutant from heme auxotrophy. The two sequences show similarity to the recently published Arabidopsis PPOX, Bacillus subtilis hemY, and to mammalian sequences encoding protoporphyrinogen IX oxidase. One cDNA sequence encodes a 548-amino acid residues protein with a putative transit sequence of 50 amino acid residues, and the second cDNA encodes a protein of 504 amino acid residues. Both deduced protein sequences share 27.2% identical amino acid residues. The first in vitro translated protoporphyrinogen IX oxidase could be translocated to plastids, and the approximately 53-kDa mature protein was detected in stroma and membrane fraction. The second enzyme was targeted to mitochondria without any detectable reduction in size. Localization of both enzymes in subcellular fractions was immunologically confirmed. Steady-state RNA analysis indicates an almost synchronous expression of both genes during tobacco plant development, greening of young seedlings, and diurnal and circadian growth. The mature plastidal and the mitochondrial isoenzyme were overexpressed in E. coli. Bacterial extracts containing the recombinant mitochondrial enzyme exhibit high protoporphyrinogen IX oxidase activity relative to control strains, whereas the plastidal enzyme could only be expressed as an inactive peptide. The data presented confirm a compartmentalized pathway of tetrapyrrole synthesis with protoporphyrinogen IX oxidase in plastids and mitochondria.

On the reaction mechanism of l-lactate oxidase: Quantitative structure-activity analysis of the reaction with para-substituted l-mandelates

The rate constants for reduction of the flavoenzyme, l-lactate oxidase, and a mutant (in which alanine 95 is replaced by glycine), by a series of para-substituted mandelates, in both the 2-1H- and 2-2H- forms, have been measured by rapid reaction spectrophotometry. In all cases, significant isotope effects (1H/2H = 3–7) on the rate constants of flavin reduction were found, indicating that flavin reduction is a direct measure of α-C-H bond breakage. The rate constants show only a small influence of the electronic characteristics of the substituents, but show a good correlation when combined with some substituent volume parameters. A surprisingly good correlation is found with the molecular mass of the substrate. The results are compatible with any mechanism in which there is little development of charge in the transition state. This could be a transfer of hydride to the flavin N(5) position or a synchronous mechanism in which the α-C-H is formally abstracted as a H+ while the resulting charge is simultaneously neutralized by another event.

Analysis of exocytosis mutants indicates close coupling between regulated secretion and transcription activation in Tetrahymena

Stimulation of regulated secretory cells promotes protein release via the fusion of cytoplasmic storage vesicles with the plasma membrane. In Tetrahymena thermophila, brief exposure to secretagogue results in synchronous fusion of the entire set of docked dense-core granules with the plasma membrane. We show that stimulation is followed by rapid new dense-core granule synthesis involving gene induction. Two genes encoding granule matrix proteins, GRL1 and GRL4, are shown to undergo induction following stimulation, resulting in ≈10-fold message accumulation within 1 h. The mechanism of induction involves transcriptional regulation, and the upstream region of GRL1 functions in vivo as an inducible promoter in a heterologous reporter construct using the gene encoding green fluorescent protein. Taking advantage of the characterized exocytosis (exo−) mutants available in this system, we asked whether the signals for regranulation were generated directly by the initial stimulation, or whether downstream events were required for transcription activation. Three mutants, with defects at three distinct stages in the regulated secretory pathway, failed to show induction of GRL1 and GRL4 after exposure to secretagogue. These results argue that regranulation depends upon signals generated by the final steps in exocytosis.

Multipotent neural precursors can differentiate toward replacement of neurons undergoing targeted apoptotic degeneration in adult mouse neocortex

Neurons undergoing targeted photolytic cell death degenerate by apoptosis. Clonal, multipotent neural precursor cells were transplanted into regions of adult mouse neocortex undergoing selective degeneration of layer II/III pyramidal neurons via targeted photolysis. These precursors integrated into the regions of selective neuronal death; 15 ± 7% differentiated into neurons with many characteristics of the degenerated pyramidal neurons. They extended axons and dendrites and established afferent synaptic contacts. In intact and kainic acid-lesioned control adult neocortex, transplanted precursors differentiated exclusively into glia. These results suggest that the microenvironmental alterations produced by this synchronous apoptotic neuronal degeneration in adult neocortex induced multipotent neural precursors to undergo neuronal differentiation which ordinarily occurs only during embryonic corticogenesis. Studying the effects of this defined microenvironmental perturbation on the differentiation of clonal neural precursors may facilitate identification of factors involved in commitment and differentiation during normal development. Because photolytic degeneration simulates some mechanisms underlying apoptotic neurodegenerative diseases, these results also suggest the possibility of neural precursor transplantation as a potential cell replacement or molecular support therapy for some diseases of neocortex, even in the adult.

Operative GABAergic inhibition in hippocampal CA1 pyramidal neurons in experimental epilepsy

Patch–clamp recordings of CA1 interneurons and pyramidal cells were performed in hippocampal slices from kainate- or pilocarpine-treated rat models of temporal lobe epilepsy. We report that γ-aminobutyric acid (GABA)ergic inhibition in pyramidal neurons is still functional in temporal lobe epilepsy because: (i) the frequency of spontaneous GABAergic currents is similar to that of control and (ii) focal electrical stimulation of interneurons evokes a hyperpolarization that prevents the generation of action potentials. In paired recordings of interneurons and pyramidal cells, synchronous interictal activities were recorded. Furthermore, large network-driven GABAergic inhibitory postsynaptic currents were present in pyramidal cells during interictal discharges. The duration of these interictal discharges was increased by the GABA type A antagonist bicuculline. We conclude that GABAergic inhibition is still present and functional in these experimental models and that the principal defect of inhibition does not lie in a complete disconnection of GABAergic interneurons from their glutamatergic inputs.

Recurrent excitatory postsynaptic potentials induced by synchronized fast cortical oscillations

Gamma frequency (about 20–70 Hz) oscillations occur during novel sensory stimulation, with tight synchrony over distances of at least 7 mm. Synchronization in the visual system has been proposed to reflect coactivation of different parts of the visual field by a single spatially extended object. We have shown that intracortical mechanisms, including spike doublet firing by interneurons, can account for tight long-range synchrony. Here we show that synchronous gamma oscillations in two sites also can cause long-lasting (>1 hr) potentiation of recurrent excitatory synapses. Synchronous oscillations lasting >400 ms in hippocampal area CA1 are associated with an increase in both excitatory postsynaptic potential (EPSP) amplitude and action potential afterhyperpolarization size. The resulting EPSPs stabilize and synchronize a prolonged beta frequency (about 10–25 Hz) oscillation. The changes in EPSP size are not expressed during non-oscillatory behavior but reappear during subsequent gamma-oscillatory events. We propose that oscillation-induced EPSPs serve as a substrate for memory, whose expression either enhances or blocks synchronization of spatially separated sites. This phenomenon thus provides a dynamical mechanism for storage and retrieval of stimulus-specific neuronal assemblies.

Patch-clamp and amperometric recordings from norepinephrine transporters: Channel activity and voltage-dependent uptake

Transporters for the biogenic amines dopamine, norepinephrine, epinephrine and serotonin are largely responsible for transmitter inactivation after release. They also serve as high-affinity targets for a number of clinically relevant psychoactive agents, including antidepressants, cocaine, and amphetamines. Despite their prominent role in neurotransmitter inactivation and drug responses, we lack a clear understanding of the permeation pathway or regulation mechanisms at the single transporter level. The resolution of radiotracer-based flux techniques limits the opportunities to dissect these problems. Here we combine patch-clamp recording techniques with microamperometry to record the transporter-mediated flux of norepinephrine across isolated membrane patches. These data reveal voltage-dependent norepinephrine flux that correlates temporally with antidepressant-sensitive transporter currents in the same patch. Furthermore, we resolve unitary flux events linked with bursts of transporter channel openings. These findings indicate that norepinephrine transporters are capable of transporting neurotransmitter across the membrane in discrete shots containing hundreds of molecules. Amperometry is used widely to study neurotransmitter distribution and kinetics in the nervous system and to detect transmitter release during vesicular exocytosis. Of interest regarding the present application is the use of amperometry on inside-out patches with synchronous recording of flux and current. Thus, our results further demonstrate a powerful method to assess transporter function and regulation.