Digital Baseband Predistortion Based Linearized Broadband Inverse Class-E Power Amplifier

A newly introduced inverse class-E power amplifier (PA) was designed, simulated, fabricated, and characterized. The PA operated at 2.26 GHz and delivered 20.4-dBm output power with peak drain efficiency (DE) of 65% and power gain of 12 dB. Broadband performance was achieved across a 300-Mitz bandwidth with DE of better than 50% and 1-dB output-power flatness. The concept of enhanced injection predistortion with a capability to selectively suppress unwanted sub-frequency components and hence suitable for memory effects minimization is described coupled with a new technique that facilitates an accurate measurement of the phase of the third-order intermodulation (IM3) products. A robust iterative computational algorithm proposed in this paper dispenses with the need for manual tuning of amplitude and phase of the IM3 injected signals as commonly employed in the previous publications. The constructed inverse class-E PA was subjected to a nonconstant envelope 16 quadrature amplitude modulation signal and was linearized using combined lookup table (LUT) and enhanced injection technique from which superior properties from each technique can be simultaneously adopted. The proposed method resulted in 0.7% measured error vector magnitude (in rms) and 34-dB adjacent channel leakage power ratio improvement, which was 10 dB better than that achieved using the LUT predistortion alone.

On the Study of Network Coded AF Transmission Protocol for Wireless Multiple Access Channels

In this paper, the performance of the network coded amplify-forward cooperative protocol is studied. The use of network coding can suppress the bandwidth resource consumed by relay transmission, and hence increase the spectral efficiency of cooperative diversity. A distributed strategy of relay selection is applied to the cooperative scheme, which can reduce system overhead and also facilitate the development of the explicit expressions of information metrics, such as outage probability and ergodic capacity. Both analytical and numerical results demonstrate that the proposed protocol can achieve large ergodic capacity and full diversity gain simultaneously.

Planar High-Gain WLAN PCB Antenna

A simple design for a low-profile high-gain planar antenna has been presented in the letter. The antenna has the realized gain between 9 and 11 dBi and the return loss better than 10 dB over the 5.6-6.3-GHz frequency band, i.e. 11% bandwidth. A numerical study highlighting effects of key geometrical parameters on the gain and return loss of the antenna has been performed. It has been shown as well that the presented antenna occupies area 20% smaller than a conventional microstrip patch antenna array with a similar gain.

325GHz Single Layer Sub-Millimeter Wave FSS Based Split Ring Linear to Circular Polarisation Convertor

A single layer, frequency selective surface based, sub-millimeter wave transmission polarizer is presented that converts incident slant linear 45° polarization into circular polarization upon transmission. The polarization convertor consists of a 30 mm diameter 10 thick silicon reinforced metalized screen containing 2700 resonator cells and perforated with nested split ring slot apertures. The screen was designed and optimized using CST Microwave Studio and predictions were validated experimentally by transmission measurements over the 250-365 GHz frequency range. This frequency range is used for remote environmental monitoring and 325 GHz represents a molecular emission line for H2O. The results obtained show good agreement between measured and modeled predictions. The measured 3 dB axial ratio bandwidth was 11.75%, measured minimum Axial Ratio was 0.19 dB and the measured insertion loss of the single layer screen was 3.38 dB

Power-Combining Class-E Amplifier With Finite Choke

A recently introduced power-combining scheme for a Class-E amplifier is, for the first time, experimentally validated in this paper. A small value choke of 2.2 nH was used to substitute for the massive dc-feed inductance required in the classic Class-E circuit. The power-combining amplifier presented, which operates from a 3.2-V dc supply voltage, is shown to be able to deliver a 24-dBm output power and a 9.5-dB gain, with 64% drain efficiency and 57% power-added efficiency at 2.4 GHz. The power amplifier exhibits a 350-MHz bandwidth within which a drain efficiency that is better than 60% and an output power that is higher than 22 dBm were measured. In addition, by adopting three-harmonic termination strategy, excellent second-and third-harmonic suppression levels of 50 and 46 dBc, respectively, were obtained. The complete design cycle from analysis through fabrication to characterization is explained. © 2010 IEEE.

Screening wall effects of a thin fluidized bed by near-infrared imaging

Near-infrared (NIR) imaging was used to observe water vapour flow in a gas-solid fluidized bed reactor. The technique consisted of a broadband light, an optical filter with a bandwidth centred on strong water vapour absorptions, a Vidicon NIR camera, a nozzle from which an optically active mixture of gas and water vapour was trans-illuminated by an NIR beam and collected data of transmittance were normalized to actual optical path. The procedure was applied to a thin fluidized bed reactor with a low aspect ratio of tube to particle diameters (D-1/d(p)) in order to validate the wall effect on flow dynamics and mass transfer during the reduction of ceria-silica by hydrogen. High concentrations of water vapour emerged in the vicinity of the wall when the bed was operated at pseudo-static conditions but disappeared when the bed was run at minimum bubbling conditions. This result shows the capability of optical methods with affordable costs to 2D imaging opaque packed bed by using a spatially resolved probe located at the exit, which is of great benefit for in situ visualization of anisotropic concentrations in packed beds under industrially relevant conditions and thus for elucidation of the underlying reaction mechanism and diffusion interactions. Crown Copyright (c) 2011 Published by Elsevier B.V. All rights reserved.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

Sub-Wavelength Profile 2-D Leaky-Wave Antennas With Two Periodic Layers

A fast and accurate analysis and synthesis technique for high-gain sub-wavelength 2-D Fabry-Perot leaky-wave antennas (LWA) consisting of two periodic metallodielectric arrays over a ground plane is presented. Full-wave method of moments (MoM) together with reciprocity is employed for the estimation of the near fields upon plane wave illumination and the extraction of the radiation patterns of the LWA. This yields a fast and rigorous tool for the characterisation of this type of antennas. A thorough convergence study for different antenna designs is presented and the operation principles of these antennas as well as the radiation characteristics are discussed. Moreover, design guidelines to tailor the antenna profile, the dimensions of the arrays as well as the antenna directivity and bandwidth are provided. A study on the radiation efficiency for antennas with different profiles is also presented and the trade off between directivity and radiation bandwidth is discussed. Numerical examples are given throughout to demonstrate the technique. A finite size antenna model is simulated using commercial software (CST Microstripes 2009) which validates the technique.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Quality factor of E-plane periodically loaded waveguide resonators and filter applications

The quality factor of microwave resonators miniaturised by virtue of periodic loading is assessed. Five X-band resonators in E-plane technology with different miniaturisation factors have been designed to resonate at approximately the same frequency. The loaded quality factor is extracted from the fractional bandwidth and subsequently employed to estimate the unloaded quality factor. The study reveals that the unloaded quality factor drops approximately linearly with the miniaturisation. Subsequently design guidelines for E-plane filters with periodically loaded resonators are provided by means of an example involving a fifth-order filter. Full-wave simulated and experimental results are presented to validate the study.

Adaptive Code Allocation for Interference Management on the Downlink of DS-CDMA Systems

A new technique based on adaptive code-to-user allocation for interference management on the downlink of BPSK based TDD DS-CDMA systems is presented. The principle of the proposed technique is to exploit the dependency of multiple access interference on the instantaneous symbol values of the active users. The objective is to adaptively allocate the available spreading sequences to users on a symbol-by-symbol basis to optimize the decision variables at the downlink receivers. The presented simulations show an overall system BER performance improvement of more than an order of a magnitude with the proposed technique while the adaptation overhead is kept less than 10% of the available bandwidth.

Ultrafast Low-Loss 40-70 GHz SPST Switch

The design and characterizations of an ultrafast single-pole single-throw (SPST) absorptive differential switch are presented. The switch exhibits low insertion loss less than 1 dB, and isolation better than 16 dB from 40 to 70 GHz. Sub-nanosecond switching time is achieved by adopting a differential current-steering technique. The total measured rise and fall time are 75 ps envisaging that switching rates up to 13 Gb/s are achievable. To our best knowledge, this is the fastest, lowest insertion loss V-band SPST switch yet reported that can operate over a wide bandwidth of 30 GHz.

Anisotropic Impedance Surfaces for Linear to Circular Polarization Conversion

Anisotropic impedance surfaces are employed as low-profile and broadband reflectors that convert orthogonal linear to right- and left-handed circular polarization respectively. By virtue of anisotropy, it is possible to independently control the reflection characteristics of two orthogonal linearly polarized incident plane waves and therefore achieve linear to circular polarization conversion. Equivalent circuits for anisotropic impedance surfaces with arbitrarily shaped elements are employed to demonstrate the operating principle and a design procedure is proposed. The proposed design procedure is demonstrated by means of an example involving a dipole array. A prototype is designed and its performance characteristics are evaluated. The 3-dB relative axial ratio bandwidth exceeds 60%, while low loss and angular stability are also reported. Numerical and experimental results on a fabricated prototype are presented to validate the synthesis and the performance. © 2006 IEEE.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Frequency selective surface using nested split ring slot elements as a lens with mechanically reconfigurable beam steering capability

The design is described of a double layer frequency selective surface which can produce a differential phase shift of 180 ° as the wave propagates through it at normal incidence. The hand of an applied circularly polarized signal is reversed due to the 180° phase shift, and it is demonstrated that the exit circularly polarized output signal can be phase advanced or phase retarded by 180 ° upon rotation of the elements comprising the structure. This feature allows the surface to act as a spatial phase shifter. In this paper the beam steering capabilities of a 10 × 10 array of such elements are demonstrated. Here the individual elements comprising the array are rotated relative to each other in order to generate a progressive phase shift. At normal incidence the 3 dB Axial Ratio Bandwidth for LHCP to RHCP conversion is 5.3% and the insertion loss was found to be -2.3 dB, with minimum axial ratio of 0.05 dB. This array is shown to be able to steer a beam from -40 ° to +40 ° while holding axial ratio at the pointing angle to below 4 dB. The measured radiation patterns match the theoretical calculation and full-wave simulation results. © 2010 IEEE.