Videolaparoscopia no trauma abdominal

Despite the use of laparoscopy in abdominal trauma for several decades, it was only after the advent of video chip camera that an explosion of interest ocurred, giving rise to possibilities and perspectives not only in diagnosis but also in therapeutics. In trauma, its use has been gradually defined and experience has shown the benefits of the method in early diagnosis of visceral injuries as well as avoiding unnecessary laparotomies. Trauma laparoscopy is a safe method, can reduce negative and nontherapeutic laparotomies. The worrisome failure of laparoscopy to detect gastrintestinal injuries, specially small bowel lesions can be avoided with a mandatory and apropriated "run bowel" exploration. We believe that in hemodinamically stable patients, video laparoscopy is safely indicated in some situations in trauma, such as evaluation of diaphragmatic injuries in thoraco abdominal stab wounds and tangential gunshot wounds of anterior abdominal wall.

Improving strategic decision-making with simulation based decision support systems

Combating climate change is one of the key tasks of humanity in the 21st century. One of the leading causes is carbon dioxide emissions due to usage of fossil fuels. Renewable energy sources should be used instead of relying on oil, gas, and coal. In Finland a significant amount of energy is produced using wood. The usage of wood chips is expected to increase in the future significantly, over 60 %. The aim of this research is to improve understanding over the costs of wood chip supply chains. This is conducted by utilizing simulation as the main research method. The simulation model utilizes both agent-based modelling and discrete event simulation to imitate the wood chip supply chain. This thesis concentrates on the usage of simulation based decision support systems in strategic decision-making. The simulation model is part of a decision support system, which connects the simulation model to databases but also provides a graphical user interface for the decisionmaker. The main analysis conducted with the decision support system concentrates on comparing a traditional supply chain to a supply chain utilizing specialized containers. According to the analysis, the container supply chain is able to have smaller costs than the traditional supply chain. Also, a container supply chain can be more easily scaled up due to faster emptying operations. Initially the container operations would only supply part of the fuel needs of a power plant and it would complement the current supply chain. The model can be expanded to include intermodal supply chains as due to increased demand in the future there is not enough wood chips located close to current and future power plants.

Spin-Dynamics in Cold Gases of 87Rb and Atomic Hydrogen. The spins they are a-changin’

In this thesis the dynamics of cold gaseous atoms is studied. Two different atomic species and two different experimental techniques have been used. In the first part of the thesis experiments with Bose-Einstein condensates of Rb-87 are presented. In these experiments the methods of laser cooling and magnetic trapping of atoms were utilized. An atom chip was used as the experimental technique for implementation of magnetic trapping. The atom chip is a small integrated instrument allowing accurate and detailed manipulation of the atoms. The experiments with Rb-87 probed the behaviour of a falling beam of atoms outcoupled from the Bose-Einstein condensate by electromagnetic field induced spin flips. In the experiments a correspondence between the phases of the outcoupling radio frequency field and the falling beam of atoms was found. In the second part of the thesis experiments of spin dynamics in cold atomic hydrogen gas are discussed. The experiments with atomic hydrogen are conducted in a cryostat using a dilution refrigerator as the cooling method. These experiments concentrated on explaining and quantifying modulations in the electron spin resonance spectra of doubly polarized atomic hydrogen. The modifications to the previous experimental setup are described and the observation of electron spin waves is presented. The observed spin wave modes were caused by the identical spin rotation effect. These modes have a strong dependence on the spatial profile of the polarizing magnetic field. We also demonstrated confinement of these modes in regions of strong magnetic field and manipulated their spatial distribution by changing the position of the field maximum.

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.

Adaptive Routing Approaches for Networked Many-Core Systems

Through advances in technology, System-on-Chip design is moving towards integrating tens to hundreds of intellectual property blocks into a single chip. In such a many-core system, on-chip communication becomes a performance bottleneck for high performance designs. Network-on-Chip (NoC) has emerged as a viable solution for the communication challenges in highly complex chips. The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and NoC schemes provide the possibility of designing a high performance system in a limited chip area. The major advantages of 3D NoCs are the considerable reductions in average latency and power consumption. There are several factors degrading the performance of NoCs. In this thesis, we investigate three main performance-limiting factors: network congestion, faults, and the lack of efficient multicast support. We address these issues by the means of routing algorithms. Congestion of data packets may lead to increased network latency and power consumption. Thus, we propose three different approaches for alleviating such congestion in the network. The first approach is based on measuring the congestion information in different regions of the network, distributing the information over the network, and utilizing this information when making a routing decision. The second approach employs a learning method to dynamically find the less congested routes according to the underlying traffic. The third approach is based on a fuzzy-logic technique to perform better routing decisions when traffic information of different routes is available. Faults affect performance significantly, as then packets should take longer paths in order to be routed around the faults, which in turn increases congestion around the faulty regions. We propose four methods to tolerate faults at the link and switch level by using only the shortest paths as long as such path exists. The unique characteristic among these methods is the toleration of faults while also maintaining the performance of NoCs. To the best of our knowledge, these algorithms are the first approaches to bypassing faults prior to reaching them while avoiding unnecessary misrouting of packets. Current implementations of multicast communication result in a significant performance loss for unicast traffic. This is due to the fact that the routing rules of multicast packets limit the adaptivity of unicast packets. We present an approach in which both unicast and multicast packets can be efficiently routed within the network. While suggesting a more efficient multicast support, the proposed approach does not affect the performance of unicast routing at all. In addition, in order to reduce the overall path length of multicast packets, we present several partitioning methods along with their analytical models for latency measurement. This approach is discussed in the context of 3D mesh networks.

Hakkeen kuivaus ennen varastointia ja biopolttoaineterminaalin suunnittelu

Lempäälään aiotaan rakentaa uusi kaukolämpölaitos, jossa polttoaineena käytettäisiin haketta. Nykyään Lempäälässä tuotetaan kaukolämpöä maakaasulla, jonka käyttämisestä halutaan siirtyä käyttämään lähialueilta saatavaa biopolttoainetta. Tässä työssä halutaan selvittää, mitä hyötyjä saataisiin hakkeen koneellisesta kuivauksesta. Työn toisena tavoitteena on suunnitella ja pohtia biopolttoaineterminaalin rakentamista sekä käsitellä hakkeen varastointia yleensä. Työssä tutustutaan hakkeeseen aiheesta kertovan kirjallisuuden avulla. Työssä on myös laskettu hakkeen kuivauksesta saatavia hyötyjä hakkeen lämpöarvoon sekä energiatiheyteen. Erityisesti perehdytään metsätähdehakkeeseen, rankahakkeeseen, kuorihakkeeseen sekä sahanpuruun. Laskelmien tuloksista on havaittu, että suurin hyöty hakkeen energiatiheyden parantumisessa saadaan kun hake kuivataan 35 % kosteuspitoisuuteen. Tämän jälkeen energiatiheyden paraneminen tapahtuu hitaammin. Hakkeen kuivauksesta saadaan myös muita hyötyjä kuin energiatiheyden paraneminen. Kuivan hakkeen käsittelyn ja varastoinnin on havaittu olevan vaivattomampaa kuin märän hakkeen. Biopolttoaineterminaalin ja voimalaitoksen tulisi sijaita rinnakkain, jotta hakkeen kuivauksesta saadaan mahdollisimman kustannustehokasta. Näin ollen syntyisi myös säästöjä hakkeen kuljetuksen suhteen. Biopolttoaineterminaalin rakentamista varten tarvittaisiin tilaa alustavien laskelmien perusteella noin yksi hehtaari. Työssä on myös laskettu biopolttoaineterminaalin rakentamisesta aiheutuvia kustannuksia sekä hakkeen kuljetuksesta koituvia logistiikka kustannuksia. Haketerminaalin ja voimalaitoksen sijaintia Lempäälässä on myös kartoitettu.

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.

Reusable formal architectures for networked systems

Today's networked systems are becoming increasingly complex and diverse. The current simulation and runtime verification techniques do not provide support for developing such systems efficiently; moreover, the reliability of the simulated/verified systems is not thoroughly ensured. To address these challenges, the use of formal techniques to reason about network system development is growing, while at the same time, the mathematical background necessary for using formal techniques is a barrier for network designers to efficiently employ them. Thus, these techniques are not vastly used for developing networked systems. The objective of this thesis is to propose formal approaches for the development of reliable networked systems, by taking efficiency into account. With respect to reliability, we propose the architectural development of correct-by-construction networked system models. With respect to efficiency, we propose reusable network architectures as well as network development. At the core of our development methodology, we employ the abstraction and refinement techniques for the development and analysis of networked systems. We evaluate our proposal by employing the proposed architectures to a pervasive class of dynamic networks, i.e., wireless sensor network architectures as well as to a pervasive class of static networks, i.e., network-on-chip architectures. The ultimate goal of our research is to put forward the idea of building libraries of pre-proved rules for the efficient modelling, development, and analysis of networked systems. We take into account both qualitative and quantitative analysis of networks via varied formal tool support, using a theorem prover the Rodin platform and a statistical model checker the SMC-Uppaal.

M-käsittelyn vaikutus lastuamalla valmistettavan tuotteen valmistuskustannuksiin

Paremmin lastuttavia M-käsiteltyjä teräksiä on käytetty yrityksissä jo yli 20 vuoden ajan. Ominaisuuksiensa ansiosta M-teräksillä on pystytty pienentämään koneistuskustannuksia ja parantamaan kilpailukykyä. Viime vuosien aikana lastuavat terät ja työstökoneet ovat kuitenkin kehittyneet ja ero M-terästen ja tavanomaisten terästen välillä on voinut kaventua. Tämän diplomityön tavoitteena oli tutkia, saavutetaanko M-teräksen käytöllä taloudellisia etuja nykyaikaisissa konepajaolosuhteissa. Tutkimuksessa vertailtiin M-käsitellyn ja tavanomaisen 42CrMo4 – teräksen koneistusta. Valmistuskokeissa tarkasteltiin terien kulumista, lastun muotoa ja pinnanlaatua. Koekappaleena toimi olakkeellinen kuusiomutteri M64 kierteellä. Tuotteita valmistettiin yli 500 kappaletta ja materiaalia poistettiin noin 2000 kg. Koetulosten perusteella tuotteille laskettiin koneistuskustannukset kuvitteellisessa yrityksessä. Ero materiaalien välillä oli suurin työvaiheissa, joissa lastuaminen oli jatkuvaa. Sisä- ja ulkosorvauksessa M-käsiteltyä terästä lastunneiden terien kestoikä oli noin kaksinkertainen ja kierteen sorvauksessa noin nelinkertainen tavalliseen teräkseen verrattuna. Hakkaavassa työstössä terien kestoikä oli molemmilla materiaaleilla sama. Työssä suoritettujen kokeiden ja kustannuslaskelmien perusteella, käyttämällä M-käsiteltyä terästä voidaan pienentää valmistuskustannuksia. Materiaalien välinen ero korostuu, kun hakkaavaa työstöä on vähän, sarjat ovat suuria ja tuotanto on miehittämätöntä.

Readout Electronics for Gas Electron Multiplier Detectors

The European Organization for Nuclear Research (CERN) operates the largest particle collider in the world. This particle collider is called the Large Hadron Collider (LHC) and it will undergo a maintenance break sometime in 2017 or 2018. During the break, the particle detectors, which operate around the particle collider, will be serviced and upgraded. Following the improvement in performance of the particle collider, the requirements for the detector electronics will be more demanding. In particular, the high amount of radiation during the operation of the particle collider sets requirements for the electronics that are uncommon in commercial electronics. Electronics that are built to function in the challenging environment of the collider have been designed at CERN. In order to meet the future challenges of data transmission, a GigaBit Transceiver data transmission module and an E-Link data bus have been developed. The next generation of readout electronics is designed to benefit from these technologies. However, the current readout electronics chips are not compatible with these technologies. As a result, in addition to new Gas Electron Multiplier (GEM) detectors and other technology, a new compatible chip is developed to function within the GEMs for the Compact Muon Solenoid (CMS) project. In this thesis, the objective was to study a data transmission interface that will be located on the readout chip between the E-Link bus and the control logic of the chip. The function of the module is to handle data transmission between the chip and the E-Link. In the study, a model of the interface was implemented with the Verilog hardware description language. This process was simulated by using chip design software by Cadence. State machines and operating principles with alternative possibilities for implementation are introduced in the E-Link interface design procedure. The functionality of the designed logic is demonstrated in simulation results, in which the implemented model is proven to be suitable for its task. Finally, suggestions that should be considered for improving the design have been presented.

On the numerical simulation of machining processes

Numerical simulation of machining processes can be traced back to the early seventies when finite element models for continuous chip formation were proposed. The advent of fast computers and development of new techniques to model large plastic deformations have favoured machining simulation. Relevant aspects of finite element simulation of machining processes are discussed in this paper, such as solution methods, material models, thermo-mechanical coupling, friction models, chip separation and breakage strategies and meshing/re-meshing strategies.

Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.

Transcriptional and Epigenetic Regulation of Human CD4+ T Helper Lineage Specification

Activated T helper (Th) cells have ability to differentiate into functionally distinct Th1, Th2 and Th17 subsets through a series of overlapping networks that include signaling and transcriptional control and the epigenetic mechanisms to direct immune responses. However, inappropriate execution in the differentiation process and abnormal function of these Th cells can lead to the development of several immune mediated diseases. Therefore, the thesis aimed at identifying genes and gene regulatory mechanisms responsible for Th17 differentiation and to study epigenetic changes associated with early stage of Th1/Th2 cell differentiation. Genome wide transcriptional profiling during early stages of human Th17 cell differentiation demonstrated differential regulation of several novel and currently known genes associated with Th17 differentiation. Selected candidate genes were further validated at protein level and their specificity for Th17 as compared to other T helper subsets was analyzed. Moreover, combination of RNA interference-mediated downregulation of gene expression, genome-wide transcriptome profiling and chromatin immunoprecipitation followed by massive parallel sequencing (ChIP-seq), combined with computational data integration lead to the identification of direct and indirect target genes of STAT3, which is a pivotal upstream transcription factor for Th17 cell polarization. Results indicated that STAT3 directly regulates the expression of several genes that are known to play a role in activation, differentiation, proliferation, and survival of Th17 cells. These results provide a basis for constructing a network regulating gene expression during early human Th17 differentiation. Th1 and Th2 lineage specific enhancers were identified from genome-wide maps of histone modifications generated from the cells differentiating towards Th1 and Th2 lineages at 72h. Further analysis of lineage-specific enhancers revealed known and novel transcription factors that potentially control lineage-specific gene expression. Finally, we found an overlap of a subset of enhancers with SNPs associated with autoimmune diseases through GWASs suggesting a potential role for enhancer elements in the disease development. In conclusion, the results obtained have extended our knowledge of Th differentiation and provided new mechanistic insights into dysregulation of Th cell differentiation in human immune mediated diseases.

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.

Puuhakkeen käsittely- ja poltto-ominaisuuksien parantaminen

Nykyaikana yhteiskunta tavoittelee uusiutuvaa ja ympäristöä säästävää energiantuotantoa. Biopolttoaineiden käyttö vähentää fossiilisten polttoaineiden osuutta energiantuotannossa. Jotta biopolttoaineilla voidaan korvata fossiilisia polttoaineita, biopolttoaineita täytyy jalostaa. Tämän diplomityön tarkoituksena on selvittää puuhakkeen jalostuksen merkitystä hakkeen käytölle ja kannattavuudelle. Hakkeen kuivaamisella ja seulonnalla voidaan parantaa hakkeen käsittely- ja poltto-ominaisuuksia. Kosteuden ja tasalaatuisuuden merkitys suurenee, kun haketta käytetään pienissä kattiloissa. Pienissä kattiloissa lämmöntuotannon hyötysuhde pienenee merkittävästi kosteuden suurentuessa. Tällöin polttoaineen kulutus ja energiantuotantokustannukset suurenevat. Suuremmissa kattiloissa hyvälaatuisella hakkeella on mahdollista korvata kalliimpia vara- ja huippukuormapolttoaineita, kuten öljyä. Tällöin fossiilisten polttoaineiden osuus pienenee. Lisäksi kuivaaminen ja seulominen ovat edullisia jalostusprosesseja esimerkiksi pelletin tuotantoon verrattuna.