Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

PUE attack detection in CWSN using collaboration and learning behavior

Cognitive Wireless Sensor Network (CWSN) is a new paradigm which integrates cognitive features in traditional Wireless Sensor Networks (WSNs) to mitigate important problems such as spectrum occupancy. Security in Cognitive Wireless Sensor Networks is an important problem because these kinds of networks manage critical applications and data. Moreover, the specific constraints of WSN make the problem even more critical. However, effective solutions have not been implemented yet. Among the specific attacks derived from new cognitive features, the one most studied is the Primary User Emulation (PUE) attack. This paper discusses a new approach, based on anomaly behavior detection and collaboration, to detect the PUE attack in CWSN scenarios. A nonparametric CUSUM algorithm, suitable for low resource networks like CWSN, has been used in this work. The algorithm has been tested using a cognitive simulator that brings important results in this area. For example, the result shows that the number of collaborative nodes is the most important parameter in order to improve the PUE attack detection rates. If the 20% of the nodes collaborates, the PUE detection reaches the 98% with less than 1% of false positives.

Impedance-based stability and transient-performance assessment applying maximum peak criteria

The impedance-based stability-assessment method has turned out to be a very effective tool and its usage is rapidly growing in different applications ranging from the conventional interconnected dc/dc systems to the grid-connected renewable energy systems. The results are sometime given as a certain forbidden region in the complex plane out of which the impedance ratio--known as minor-loop gain--shall stay for ensuring robust stability. This letter discusses the circle-like forbidden region occupying minimum area in the complex plane, defined by applying maximum peak criteria, which is well-known theory in control engineering. The investigation shows that the circle-like forbidden region will ensure robust stability only if the impedance-based minor-loop gain is determined at the very input or output of each subsystem within the interconnected system. Experimental evidence is provided based on a small-scale dc/dc distributed system.

Effects of cross sections tables generation and optimization on rod ejection transient analyses

Best estimate analysis of rod ejection transients requires 3D kinetics core simulators. If they use cross sections libraries compiled in multidimensional tables,interpolation errors – originated when the core simulator computes the cross sections from the table values – are a source of uncertainty in k-effective calculations that should be accounted for. Those errors depend on the grid covering the domain of state variables and can be easily reduced, in contrast with other sources of uncertainties such as the ones due to nuclear data, by choosing an optimized grid distribution. The present paper assesses the impact of the grid structure on a PWR rod ejection transient analysis using the coupled neutron-kinetics/thermal-hydraulicsCOBAYA3/COBRA-TF system. Forthispurpose, the OECD/NEA PWR MOX/UO2 core transient benchmark has been chosen, as material compositions and geometries are available, allowing the use of lattice codes to generate libraries with different grid structures. Since a complete nodal cross-section library is also provided as part of the benchmark specifications, the effects of the library generation on transient behavior are also analyzed.Results showed large discrepancies when using the benchmark library and own-generated libraries when compared with benchmark participants’ solutions. The origin of the discrepancies was found to lie in the nodal cross sections provided in the benchmark.

Transient behavior of a system composed of conductive thin wire structures excited by harmonic and lightning type signals

The transient response of a system of independent electrodes buried in a semi-infinite conducting medium is studied. Using a simple and versatile numerical scheme written by the authors and based on the Electric Field Integral Equation (EFIE), the effect caused by harmonic signals ranging on frequency from Hz to hundred of MHz, and also by lightning type driving signal striking at a remote point far from the conductors, is extensively studied. The value of the scalar potential appearing on the electrodes as a function of the frequency of the applied signal is one of the variables investigated. Other features such as the input impedance at the injection point of the signal and the Ground Potential Rise (GPR) over the electrode system are also discussed

Transient thermal analysis during the ascent phase of a balloon-borne payload. Comparison with SUNRISE test flight measurements

The thermal design of stratospheric balloon payloads usually focuses on the cruise phase of the missions, that is, the floating altitude conditions. The ascent phase usually takes between 2 and 4 h, a very small period compared to the duration of the whole mission, which can last up to 4 weeks. However, during this phase payloads are subjected to very harsh conditions due mainly to the convective cooling that occurs as the balloon passes through the cold atmosphere, with minimum temperatures in the tropopause. The aim of this work is to study the thermal behaviour of a payload carried by a long duration balloon during the ascent phase. Its temperature has been calculated as a function of the altitude from sea level to floating conditions. To perform this analysis it has been assumed that the thermal interactions (convection and radiation) depend on the altitude, on the environmental conditions (which in turn depend also on the altitude) and on the temperature of the system itself. The results have been compared with the measurements taken during the SUNRISE test flight, launched in October 2007 by CSBF from Fort Sumner (New Mexico).

Transient excess of MYC activity can elicit genomic instability and tumorigenesis

Overexpression of the MYC protooncogene has been implicated in the genesis of diverse human tumors. Tumorigenesis induced by MYC has been attributed to sustained effects on proliferation and differentiation. Here we report that MYC may also contribute to tumorigenesis by destabilizing the cellular genome. A transient excess of MYC activity increased tumorigenicity of Rat1A cells by at least 50-fold. The increase persisted for >30 days after the return of MYC activity to normal levels. The brief surfeit of MYC activity was accompanied by evidence of genomic instability, including karyotypic abnormalities, gene amplification, and hypersensitivity to DNA-damaging agents. MYC also induced genomic destabilization in normal human fibroblasts, although these cells did not become tumorigenic. Stimulation of Rat1A cells with MYC accelerated their passage through G1/S. Moreover, MYC could force normal human fibroblasts to transit G1 and S after treatment with N-(phosphonoacetyl)-l-aspartate (PALA) at concentrations that normally lead to arrest in S phase by checkpoint mechanisms. Instead, the cells subsequently appeared to arrest in G2. We suggest that the accelerated passage through G1 was mutagenic but that the effect of MYC permitted a checkpoint response only after G2 had been reached. Thus, MYC may contribute to tumorigenesis through a dominant mutator effect.

Trimming Surface Sugars Protects Histoplasma from Immune Attack

ACKNOWLEDGMENTS G.D.B. thanks the Wellcome Trust and MRC (United Kingdom) for funding.

Immunologic tolerance to myelin basic protein decreases stroke size after transient focal cerebral ischemia

Immune mechanisms contribute to cerebral ischemic injury. Therapeutic immunosuppressive options are limited due to systemic side effects. We attempted to achieve immunosuppression in the brain through oral tolerance to myelin basic protein (MBP). Lewis rats were fed low-dose bovine MBP or ovalbumin (1 mg, five times) before 3 h of middle cerebral artery occlusion (MCAO). A third group of animals was sensitized to MBP but did not survive the post-stroke period. Infarct size at 24 and 96 h after ischemia was significantly less in tolerized animals. Tolerance to MBP was confirmed in vivo by a decrease in delayed-type hypersensitivity to MBP. Systemic immune responses, characterized in vitro by spleen cell proliferation to Con A, lipopolysaccharide, and MBP, again confirmed antigen-specific immunologic tolerance. Immunohistochemistry revealed transforming growth factor β1 production by T cells in the brains of tolerized but not control animals. Systemic transforming growth factor β1 levels were equivalent in both groups. Corticosterone levels 24 h after surgery were elevated in all sham-operated animals and ischemic control animals but not in ischemic tolerized animals. These results demonstrate that antigen-specific modulation of the immune response decreases infarct size after focal cerebral ischemia and that sensitization to the same antigen may actually worsen outcome.

INAF, a protein required for transient receptor potential Ca2+ channel function

The trp gene of Drosophila encodes a subunit of a class of Ca2+-selective light-activated channels that carry the bulk of the phototransduction current. Transient receptor potential (TRP) homologs have been identified throughout animal phylogeny. In vertebrates, TRP-related channels have been suggested to mediate “store-operated Ca2+ entry,” which is important in Ca2+ homeostasis in a wide variety of cell types. However, the mechanisms of activation and regulation of the TRP channel are not known. Here, we report on the Drosophila inaF gene, which encodes a highly eye-enriched protein, INAF, that appears to be required for TRP channel function. A null mutation in this gene significantly reduces the amount of the TRP protein and, in addition, specifically affects the TRP channel function so as to nearly shut down its activity. The inaF mutation also dramatically suppresses the severe degeneration caused by a constitutively active mutation in the trp gene. Although the reduction in the amount of the TRP protein may contribute to these phenotypes, several lines of evidence support the view that inaF mutations also more directly affect the TRP channel function, suggesting that the INAF protein may have a regulatory role in the channel function.

Stimulation of the blue light phototropic receptor NPH1 causes a transient increase in cytosolic Ca2+

Blue light regulates plant growth and development, and three photoreceptors, CRY1, CRY2, and NPH1, have been identified. The transduction pathways of these receptors are poorly understood. Transgenic plants containing aequorin have been used to dissect the involvement of these three receptors in the regulation of intracellular Ca2+. Pulses of blue light induce cytosolic Ca2+ transients lasting about 80 s in Arabidopsis and tobacco seedlings. Use of organelle-targeted aequorins shows that Ca2+ increases are limited to the cytoplasm. Blue light treatment of cry1, cry2, and nph1 mutants showed that NPH1, which regulates phototropism, is largely responsible for the Ca2+ transient. The spectral response of the Ca2+ transient is similar to that of phototropism, supporting NPH1 involvement. Furthermore, known interactions between red and blue light and between successive blue light pulses on phototropic sensitivity are mirrored in the blue light control of cytosolic Ca2+ in these seedlings. Our observations raise the possibility that physiological responses regulated by NPH1, such as phototropism, may be transduced through cytosolic Ca2+.

A transient expansion of the native state precedes aggregation of recombinant human interferon-γ

Aggregation of proteins, even under conditions favoring the native state, is a ubiquitous problem in biotechnology and biomedical engineering. Providing a mechanistic basis for the pathways that lead to aggregation should allow development of rational approaches for its prevention. We have chosen recombinant human interferon-γ (rhIFN-γ) as a model protein for a mechanistic study of aggregation. In the presence of 0.9 M guanidinium hydrochloride, rhIFN-γ aggregates with first order kinetics, a process that is inhibited by addition of sucrose. We describe a pathway that accounts for both the observed first-order aggregation of rhIFN-γ and the effect of sucrose. In this pathway, aggregation proceeds through a transient expansion of the native state. Sucrose shifts the equilibrium within the ensemble of rhIFN-γ native conformations to favor the most compact native species over more expanded ones, thus stabilizing rhIFN-γ against aggregation. This phenomenon is attributed to the preferential exclusion of sucrose from the protein surface. In addition, kinetic analysis combined with solution thermodynamics shows that only a small (9%) expansion surface area is needed to form the transient native state that precedes aggregation. The approaches used here link thermodynamics and aggregation kinetics to provide a powerful tool for understanding both the pathway of protein aggregation and the rational use of excipients to inhibit the process.

Modulation of Ca2+ entry by polypeptides of the inositol 1,4,5-trisphosphate receptor (IP3R) that bind transient receptor potential (TRP): Evidence for roles of TRP and IP3R in store depletion-activated Ca2+ entry

Homologues of Drosophilia transient receptor potential (TRP) have been proposed to be unitary subunits of plasma membrane ion channels that are activated as a consequence of active or passive depletion of Ca2+ stores. In agreement with this hypothesis, cells expressing TRPs display novel Ca2+-permeable cation channels that can be activated by the inositol 1,4,5-trisphosphate receptor (IP3R) protein. Expression of TRPs alters cells in many ways, including up-regulation of IP3Rs not coded for by TRP genes, and proof that TRP forms channels of these and other cells is still missing. Here, we document physical interaction of TRP and IP3R by coimmunoprecipitation and glutathione S-transferase-pulldown experiments and identify two regions of IP3R, F2q and F2g, that interact with one region of TRP, C7. These interacting regions were expressed in cells with an unmodified complement of TRPs and IP3Rs to study their effect on agonist- as well as store depletion-induced Ca2+ entry and to test for a role of their respective binding partners in Ca2+ entry. C7 and an F2q-containing fragment of IP3R decreased both forms of Ca2+ entry. In contrast, F2g enhanced the two forms of Ca2+ entry. We conclude that store depletion-activated Ca2+ entry occurs through channels that have TRPs as one of their normal structural components, and that these channels are directly activated by IP3Rs. IP3Rs, therefore, have the dual role of releasing Ca2+ from stores and activating Ca2+ influx in response to either increasing IP3 or decreasing luminal Ca2+.

Transient cardiac expression of constitutively active Gαq leads to hypertrophy and dilated cardiomyopathy by calcineurin-dependent and independent pathways

Cardiac hypertrophy and dilatation can result from stimulation of signal transduction pathways mediated by heterotrimeric G proteins, especially Gq, whose α subunit activates phospholipase Cβ (PLCβ). We now report that transient, modest expression of a hemagglutinin (HA) epitope-tagged, constitutively active mutant of the Gq α subunit (HAα*q) in hearts of transgenic mice is sufficient to induce cardiac hypertrophy and dilatation that continue to progress after the initiating stimulus becomes undetectable. At 2 weeks, HAα*q protein is expressed at less than 50% of endogenous αq/11, and the transgenic hearts are essentially normal morphologically. Although HAα*q protein declines at 4 weeks and is undetectable by 10 weeks, the animals develop cardiac hypertrophy and dilatation and die between 8 and 30 weeks in heart failure. As the pathology develops, endogenous αq/11 rises (2.9-fold in atria; 1.8-fold in ventricles). At 2 weeks, basal PLC activity is increased 9- to 10-fold in atria but not ventricles. By 10 weeks, it is elevated in both, presumably because of the rise in endogenous αq/11. We conclude that the pathological changes initiated by early, transient HAα*q expression are maintained in part by compensatory changes in signal transduction and other pathways. Cyclosporin A (CsA) prevents hypertrophy caused by activation of calcineurin [Molkentin, J. D., Lu, J.-R., Antos, C. L., Markham, B., Richardson, J., Robbins, J., Grant, S. R. & Olson, E. N. (1998) Cell 93, 215–228]. Because HAα*q acts upstream of calcineurin, we hypothesized that HAα*q might initiate additional pathways leading to hypertrophy and dilatation. Treating HAα*q mice with CsA diminished some, but not all, aspects of the hypertrophic phenotype, suggesting that multiple pathways are involved.

Transient “deafness” accompanies auditory development during metamorphosis from tadpole to frog

During metamorphosis, ranid frogs shift from a purely aquatic to a partly terrestrial lifestyle. The central auditory system undergoes functional and neuroanatomical reorganization in parallel with the development of new sound conduction pathways adapted for the detection of airborne sounds. Neural responses to sounds can be recorded from the auditory midbrain of tadpoles shortly after hatching, with higher rates of synchronous neural activity and lower sharpness of tuning than observed in postmetamorphic animals. Shortly before the onset of metamorphic climax, there is a brief “deaf” period during which no auditory activity can be evoked from the midbrain, and a loss of connectivity is observed between medullary and midbrain auditory nuclei. During the final stages of metamorphic development, auditory function and neural connectivity are restored. The acoustic communication system of the adult frog emerges from these periods of anatomical and physiological plasticity during metamorphosis.