Evaluation of Random Delay Insertion against DPA on FPGAs

Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks. Numerous countermeasure techniques, such as Random Delay Insertion (RDI), have been proposed to reduce the risk of DPA attacks against cryptographic devices. The RDI technique was first proposed for microprocessors but it was shown to be unsuccessful when implemented on smartcards as it was vulnerable to a variant of the DPA attack known as the Sliding-Window DPA attack.Previous research by the authors investigated the use of the RDI countermeasure for Field Programmable Gate Array (FPGA) based cryptographic devices. A split-RDI technique wasproposed to improve the security of the RDI countermeasure. A set of critical parameters wasalso proposed that could be utilized in the design stage to optimize a security algorithm designwith RDI in terms of area, speed and power. The authors also showed that RDI is an efficientcountermeasure technique on FPGA in comparison to other countermeasures.In this article, a new RDI logic design is proposed that can be used to cost-efficiently implementRDI on FPGA devices. Sliding-Window DPA and realignment attacks, which were shown to beeffective against RDI implemented on smartcard devices, are performed on the improved RDIFPGA implementation. We demonstrate that these attacks are unsuccessful and we also proposea realignment technique that can be used to demonstrate the weakness of RDI implementations.

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST) to compile sentence, word, and phoneme models. The system comprises a software backend search and an FPGA-based Gaussian calculation which are covered here. In this paper, we present an efficient pipelined design implemented both as an embedded peripheral and as a scalable, parallel hardware accelerator. Both architectures have been implemented on an Alpha Data XRC-5T1, reconfigurable computer housing a Virtex 5 SX95T FPGA. The core has been tested and is capable of calculating a full set of Gaussian results from 3825 acoustic models in 9.03 ms which coupled with a backend search of 5000 words has provided an accuracy of over 80%. Parallel implementations have been designed with up to 32 cores and have been successfully implemented with a clock frequency of 133?MHz.

Self-aligning wireless link using modulated backscatter

A self-tracking (aligning) radio communications system based on the principle of modulated backscatter detection is presented here. Using amplitude-modulated backscatter from a co-operating target, a modified IQ demodulation scheme is used to reproduce automatically and in real time both the received and conjugate of the received phase of an incoming signal. The phase conjugated demodulated IF signal can have incoming backscattered data removed and new data are inserted before being up-converted using IQ single side-band generation so that retro-directive re-transmission can be made to occur. In the absence of the backscattered modulation signal, no phase conjugation and hence no retro-directed re-transmission can occur. The system reported is therefore inherently self-authenticating a facility not readily available from previously reported retro-directive self-tracking systems. © 2010 © The Institution of Engineering and Technology.

A 60 GHz wide tuning range SiGe bipolar VCO for HDMI and wireless docking applications

A wide tuning range voltage controlled oscillator (VCO) with novel architecture is proposed in this work. The entire circuit consists of a VCO core, a summing circuit, a single-ended to differential (STD) converter and a buffer amplifier. The VCO core oscillates at half the desired frequency and the second harmonic of the VCO core is extracted by the summing circuit, which is then converted to a differential pair by the STD. The entire VCO circuit operates from 58.85 to 70.85 GHz with 20% frequency tuning range. The measured VCO gain is less than 1.6 GHz/V. The measured phase noise at 3 MHz offset is less than -78 dBc/Hz across the entire tuning range. The differential phase error of the output signals is measured by down converting the VCO output signals to low gigahertz frequency using an on-chip mixer. The measured differential phase error is less than 8°. The VCO circuit, which is constructed using 0.35 µm SiGe technology, occupies 770 × 550 µm2 die area and consumes 62 mA under 3.5 V supply.

Far field subwavelength source resolution using Phase Conjugating Lens Assisted With Evanescent-to-Propagating Spectrum Conversion

The imaging properties of a phase conjugating lens operating in the far field zone of the imaged source and augmented with scatterers positioned in the source near field region are theoretically studied in this paper. The phase conjugating lens consists of a double sided 2D assembly of straight wire elements, individually interconnected through phase conjugation operators. The scattering elements are straight wire segments which are loaded with lumped impedance loads at their centers. We analytically and numerically analyze all stages of the imaging process; i) evanescent-to-propagating spectrum conversion; ii) focusing properties of infinite or finite sized phase conjugating lens; iii) source reconstruction upon propagating-to-evanescent spectrum conversion. We show that the resolution that can be achieved depends critically on the separation distance between the imaged source and scattering arrangement, as well as on the topology of the scatterers used. Imaged focal widths of up to one-seventh wavelength are demonstrated. The results obtained indicate the possibility of such an arrangement as a potential practical means for realising using conventional materials devices for fine feature extraction by electromagnetic lensing at distances remotely located from the source objects under investigation

Real-valued fixed-complexity sphere decoder for high dimensional QAM-MIMO systems

The development of high performance, low computational complexity detection algorithms is a key challenge for real-time Multiple-Input Multiple-Output (MIMO) communication system design. The Fixed-Complexity Sphere Decoder (FSD) algorithm is one of the most promising approaches, enabling quasi-ML decoding accuracy and high performance implementation due to its deterministic, highly parallel structure. However, it suffers from exponential growth in computational complexity as the number of MIMO transmit antennas increases, critically limiting its scalability to larger MIMO system topologies. In this paper, we present a solution to this problem by applying a novel cutting protocol to the decoding tree of a real-valued FSD algorithm. The new Real-valued Fixed-Complexity Sphere Decoder (RFSD) algorithm derived achieves similar quasi-ML decoding performance as FSD, but with an average 70% reduction in computational complexity, as we demonstrate from both theoretical and implementation perspectives for Quadrature Amplitude Modulation (QAM)-MIMO systems.

Quality factor of E-plane periodically loaded waveguide resonators and filter applications

The quality factor of microwave resonators miniaturised by virtue of periodic loading is assessed. Five X-band resonators in E-plane technology with different miniaturisation factors have been designed to resonate at approximately the same frequency. The loaded quality factor is extracted from the fractional bandwidth and subsequently employed to estimate the unloaded quality factor. The study reveals that the unloaded quality factor drops approximately linearly with the miniaturisation. Subsequently design guidelines for E-plane filters with periodically loaded resonators are provided by means of an example involving a fifth-order filter. Full-wave simulated and experimental results are presented to validate the study.

Power Stored and Quality Factors in Frequency Selective Surfaces at THz Frequencies

A study of the external, loaded and unloaded quality factors for frequency selective surfaces (FSSs) is presented. The study is focused on THz frequencies between 5 and 30 THz, where ohmic losses arising from the conductors become important. The influence of material properties, such as metal thickness, conductivity dispersion and surface roughness, is investigated. An equivalent circuit that models the FSS in the presence of ohmic losses is introduced and validated by means of full-wave results. Using both full-wave methods as well as a circuit model, the reactive energy stored in the vicinity of the FSS at resonance upon plane-wave incidence is presented. By studying a doubly periodic array of aluminium strips, it is revealed that the reactive power stored at resonance increases rapidly with increasing periodicity. Moreover, it is demonstrated that arrays with larger periodicity-and therefore less metallisation per unit area-exhibit stronger thermal absorption. Despite this absorption, arrays with higher periodicities produce higher unloaded quality factors. Finally, experimental results of a fabricated prototype operating at 14 THz are presented.