Growing process of CdS nanoclusters in zeolite Y studied by positron annihilation

Zeolite Y has been used as the host to generate CdS nanoclusters. The location of CdS nanoclusters inside zeolite hosts was confirmed by the blue-shifted reflection absorption spectra with respect to that of bulk CdS materials. But which kind of cage inside zeolite Y, sodalite cage or supercage, was preferred for the CdS clusters remained unclear. In this paper, we conducted positron annihilation spectroscopy (PAS) measurements for the first time on a series of CdS/Y zeolite samples and concluded that CdS clusters were not located in supercages but in smaller sodalite cages. The stability of CdS clusters inside the sodalite units was due to the coordination of Cd atoms with the framework oxygen atoms of the double six-ring windows. Moreover, PAS revealed some important information of surface states existing on the interfacial layers between CdS clusters and zeolite Y. (C) 2001 Elsevier Science B,V, All rights reserved.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).