Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

Field configured assembly: Programmed manipulation and self-assembly at the mesoscale

Field configured assembly is a programmable force field method that permits rapid, "hands-free" manipulation, assembly, and integration of mesoscale objects and devices. In this method, electric fields, configured by specific addressing of receptor and counter electrode sites pre-patterned at a silicon chip substrate, drive the field assisted transport, positioning, and localization of mesoscale devices at selected receptor locations. Using this approach, we demonstrate field configured deterministic and stochastic self-assembly of model mesoscale devices, i.e., 50 mum diameter, 670 nm emitting GaAs-based light emitting diodes, at targeted receptor sites on a silicon chip. The versatility of the field configured assembly method suggests that it is applicable to self-assembly of a wide variety of functionally integrated nanoscale and mesoscale systems.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Paralytic shellfish poisoning detection by surface plasmon resonance-based biosensors in shellfish matrixes.

The detection of paralytic shellfish poisoning (PSP) toxins in contaminated shellfish is essential for human health preservation. Ethical and technical reasons have prompted the search for new detection procedures as an alternative to the mouse bioassay. On the basis of the detection of molecular interactions by surface plasmon resonance (SPR) biosensors, an inhibition assay was developed using an anti-GTX2/3 antibody (GT13-A) and a saxitoxin-CM5 chip. This assay allowed for quantification of saxitoxin (STX), decarbamoyl saxitoxin (dcSTX), gonyautoxin 2,3 (GTX2/3), decarbamoyl gonyautoxin 2,3 (dcGTX2/3), gonyautoxin 5 (GTX5), and C 1,2 (C1/2) at concentrations from 2 to 50 ng/mL. The interference of five shellfish matrixes with the inhibition assay was analyzed. Mussels, clams, cockles, scallops, and oysters were extracted with five published methods. Ethanol extracts and acetic acid/heat extracts (AOAC Lawrence method) performed adequately in terms of surface regeneration and baseline interference, did not inhibit antibody binding to the chip surface significantly, and presented STX calibration curves similar to buffer controls in all matrixes tested. Hydrochloric acid/heat extracts (AOAC mouse bioassay method) presented surface regeneration problems, and although ethanol-acetic acid/dichloromethane extracts performed well, they were considered too laborious for routine sample testing. Overall the best results were obtained with the ethanol extraction method with calibration curves prepared in blank matrix extracts. STX recovery rate with the ethanol extraction method was 60.52 ± 3.72%, with variations among species. The performance of this biosensor assay in natural samples, compared to two AOAC methods for PSP toxin quantification (mouse bioassay and HPLC), suggests that this technology can be useful as a PSP screening assay. In summary, the GT13-A-STX chip inhibition assay is capable of PSP toxin detection in ethanol shellfish extracts, with sufficient sensitivity to quantify the toxin in the range of the European regulatory limit of 80 g/100 g of shellfish meat.

Dispersing Light with Surface Plasmon Polaritonic Crystals

Spectral dispersion of light on a finite-size surface plasmon polaritonic (SPP) crystal has been studied. The angular wavelength separation of one or more orders of magnitude higher than in other state-of-the-art wavelength-splitting devices available to date has been demonstrated. The two-stage process is responsible for the dispersion value, which involves conversion of the incident light into SPP Bloch modes of a nanostructure followed by the SPP Bloch waves refraction at the SPP crystal boundary. The high spectral dispersion achievable in plasmonic devices may be useful for integrated high-resolution spectroscopy in nanophotonic, optical communication and lab-on-a-chip applications.

A surface plasmon resonance biosensor assay for the simultaneous determination of thiamphenicol, florefenicol, florefenicol amine and chloramphenicol residues in shrimps

A rapid and sensitive screening qualitative method using a surface plasmon resonance (SPR) biosensor was developed which can detect of all fenicol antibiotic residues in shrimps from a single sample extract. This method requires ethyl acetate extraction followed by a single wash with isooctane/chlorofonrm. Each sample extract is injected over the surfaces of two biosensor chip flow cells, one surface having the capability to detect florefenicol amine (FF amine), florefenicol (FF), and thiamphenicol (TAP) and the second surface for chloramphenicol (CAP) detection. The estimated detection capabilities (CC beta) were 0. 1, 0.2, 250, and 0.5 ppb for CAP, FF, FF amine, and TAP, respectively. This quick, simple test allowed the detection of CAP residues in shrimps at the minimum required performance limit (MRPL) of 0.1 mu g kg(-1) for this compound and of FF, FF amine, and TAP below their maximum residue limits (MRLs). (c) 2006 Elsevier B.V. All rights reserved.

Comparison of flavor compounds of potato chips fried in palmolein and silicone fluid

The importance of the frying oil as a heat-transfer medium and as a source of flavor precursors for the formation of potato chip flavor was investigated. Potato slices were fried in palmolein or silicone fluid, and the volatile flavor compounds of the resulting chips were isolated onto Tenax and analyzed by gas chromatography-mass spectrometry. Although the heat-transfer coefficients of the oils did not differ significantly, their temperature profiles during frying were different, probably due to greater turbulence on placing potato slices in palmolein, leading to more efficient heat transfer. Levels of Strecker aldehydes and sulfides in chips fried in the two media were not significantly different, but levels of pyrazines were significantly higher in palmolein-fried chips. Amounts of 2,4-decadienal were also significantly higher in palmolein-fried chips, but there was no significant difference in hexanal levels between the samples.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.

Germanium on sapphire

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge, GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 µm and has a very low loss tangent (a) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing. © 2008 World Scientific Publishing Company.

Electro-thermal theory of intermodulation distortion in lossy microwave components

An analytic formulation of dynamic electro-thermally induced nonlinearity is developed for a general resistive element, yielding a self-heating circuit model based on a fractional derivative. The model explains the 10 dB/decade slope of the intermodulation products observed in two-tone testing. Two-tone testing at 400 MHz of attenuators, microwave chip terminations, and coaxial terminations is reported with tone spacing ranging from 1 to 100 Hz.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

Reduction of severe bovine serum associated matrix effects on carboxymethylated dextran coated biosensor surfaces

Surface plasmon resonance (SPR) based biosensor technology has been widely used in life science research for many applications. While the advantages of speed, ruggedness, versatility, sensitivity and reproducibility are often quoted, many researchers have experienced severe problem of non-specific binding (NSB) to chip surfaces when performing analysis of biological samples Such as bovine serum. Using the direct measurement of the bovine protein leptin, present in bovine serum samples as a model, a unique buffering system has been developed and optimised which was able to significantly reduce the non-specific interactions of bovine serum components with the carboxymethyl dextran chip (CM5) surface on a Biacore SPR The developed NSB buffering system comprised of HBS-EP buffer, containing 0.5 M NaCl, 0.005% CM-dextran pH 9.0. An average NSB reduction (n = 20) of 85.9% and 87.3% was found on an unmodified CM5 surface and a CM5 with bovine leptin immobilised on the chip surface, respectively. A reduction in NSB of up to 94% was observed on both surfaces. The concentration of the constitutive components and pH of the buffer were crucial in achieving this outcome. (C) 2008 Elsevier B.V. All rights reserved.

Quantitative mapping of aqueous microfluidic temperature with sub-degree resolution using fluorescence lifetime imaging microscopy

The use of a water-soluble, thermo-responsive polymer as a highly sensitive fluorescence-lifetime probe of microfluidic temperature is demonstrated. The fluorescence lifetime of poly(N-isopropylacrylamide) labelled with a benzofurazan fluorophore is shown to have a steep dependence on temperature around the polymer phase transition and the photophysical origin of this response is established. The use of this unusual fluorescent probe in conjunction with fluorescence lifetime imaging microscopy (FLIM) enables the spatial variation of temperature in a microfluidic device to be mapped, on the micron scale, with a resolution of less than 0.1 degrees C. This represents an increase in temperature resolution of an order of magnitude over that achieved previously by FLIM of temperature-sensitive dyes

Memory-Centric Hardware Synthesis from Dataflow Models

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.