952 resultados para in-channel dam


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Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

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A multivariate analysis on flood variables is needed to design some hydraulic structures like dams, as the complexity of the routing process in a reservoir requires a representation of the full hydrograph. In this work, a bivariate copula model was used to obtain the bivariate joint distribution of flood peak and volume, in order to know the probability of occurrence of a given inflow hydrograph. However, the risk of dam overtopping is given by the maximum water elevation reached during the routing process, which depends on the hydrograph variables, the reservoir volume and the spillway crest length. Consequently, an additional bivariate return period, the so-called routed return period, was defined in terms of risk of dam overtopping based on this maximum water elevation obtained after routing the inflow hydrographs. The theoretical return periods, which give the probability of occurrence of a hydrograph prior to accounting for the reservoir routing, were compared with the routed return period, as in both cases hydrographs with the same probability will draw a curve in the peak-volume space. The procedure was applied to the case study of the Santillana reservoir in Spain. Different reservoir volumes and spillway lengths were considered to investigate the influence of the dam and reservoir characteristics on the results. The methodology improves the estimation of the Design Flood Hydrograph and can be applied to assess the risk of dam overtopping

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La gestión de estériles de una explotación minera es un punto clave en el desarrollo económico de una actividad extractiva, y en especial, del entorno natural y social en el que se emplaza dicho proyecto. La minería de metales preciosos lleva asociada la construcción de balsas de residuos muy peligrosos, fruto de su proceso extractivo, como por ejemplo la cianuración en el caso del oro. Para un correcto funcionamiento de dichos emplazamientos es necesario escoger correctamente el método constructivo a partir de estudios de reconocimiento previos, como estudios de estabilidad geotécnica, contexto geológico de la zona, sismicidad, hidrología, etc. Así mismo, han de llevarse a cabo unas exhaustivas medidas de control y vigilancia para asegurar las condiciones de seguridad exigidas. La ruptura de la balsa de decantación de Aurul S.A. en Baia Mare (Rumania) el 30 de Enero del año 2000 ha sido escogido como caso de estudio de estabilidad de diques. ABSTRACT Tailing's management of a mining exploitation is a key point in the economical development of the extractive activity and, especially, of the natural and social environment of the site. Precious metals mining has high hazardous embankment construction associated, product of its extractive process, i.e. gold cyanidation. A correct operation of those sites makes necessary to choose a suitable construction method, based on previous studies as geotechnical stability studies, geological context of the area, seismicity, hydrology, etc. At the same time, exhaustive control and monitoring must be carried out in order to assure the required safety conditions. Aurul's decantation pond failure in Baia Mare (Romania), on 30th January 2000, has been chosen as a stability analysis case-study.

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A body with a shape similar to a hot wire with its sheath, but no prongs, has been placed close to the wall of a turbulent channel at Re_tau = 600. The results of the channel flow, without the wire, agree with previous published ones, despite the modest resolution and domain size. A simplified, two-dimensional version of the wire at the same Reynolds number has been studied to compare the dynamic response of cold and hot wires, where a slightly bigger perturbation is seen in the hot case, but an almost identical dynamic response. The cold wire seems to be able to measure instantaneous velocity with total drag after proper calibration. Being a DNS, the complete description of the flow field around the wire is obtained.

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Central core disease is a rare, nonprogressive myopathy that is characterized by hypotonia and proximal muscle weakness. In a large Mexican kindred with an unusually severe and highly penetrant form of the disorder, DNA sequencing identified an I4898T mutation in the C-terminal transmembrane/luminal region of the RyR1 protein that constitutes the skeletal muscle ryanodine receptor. All previously reported RYR1 mutations are located either in the cytoplasmic N terminus or in a central cytoplasmic region of the 5,038-aa protein. The I4898T mutation was introduced into a rabbit RYR1 cDNA and expressed in HEK-293 cells. The response of the mutant RyR1 Ca2+ channel to the agonists halothane and caffeine in a Ca2+ photometry assay was completely abolished. Coexpression of normal and mutant RYR1 cDNAs in a 1:1 ratio, however, produced RyR1 channels with normal halothane and caffeine sensitivities, but maximal levels of Ca2+ release were reduced by 67%. [3H]Ryanodine binding indicated that the heterozygous channel is activated by Ca2+ concentrations 4-fold lower than normal. Single-cell analysis of cotransfected cells showed a significantly increased resting cytoplasmic Ca2+ level and a significantly reduced luminal Ca2+ level. These data are indicative of a leaky channel, possibly caused by a reduction in the Ca2+ concentration required for channel activation. Comparison with two other coexpressed mutant/normal channels suggests that the I4898T mutation produces one of the most abnormal RyR1 channels yet investigated, and this level of abnormality is reflected in the severe and penetrant phenotype of affected central core disease individuals.

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The epithelial Na+ channel (ENaC) belongs to a new class of channel proteins called the ENaC/DEG superfamily involved in epithelial Na+ transport, mechanotransduction, and neurotransmission. The role of ENaC in Na+ homeostasis and in the control of blood pressure has been demonstrated recently by the identification of mutations in ENaC β and γ subunits causing hypertension. The function of ENaC in Na+ reabsorption depends critically on its ability to discriminate between Na+ and other ions like K+ or Ca2+. ENaC is virtually impermeant to K+ ions, and the molecular basis for its high ionic selectivity is largely unknown. We have identified a conserved Ser residue in the second transmembrane domain of the ENaC α subunit (αS589), which when mutated allows larger ions such as K+, Rb+, Cs+, and divalent cations to pass through the channel. The relative ion permeability of each of the αS589 mutants is related inversely to the ionic radius of the permeant ion, indicating that αS589 mutations increase the molecular cutoff of the channel by modifying the pore geometry at the selectivity filter. Proper geometry of the pore is required to tightly accommodate Na+ and Li+ ions and to exclude larger cations. We provide evidence that ENaC discriminates between cations mainly on the basis of their size and the energy of dehydration.

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Sensory transduction in olfactory neurons involves the activation of a cyclic nucleotide-gated (CNG) channel by cAMP. Previous studies identified a CNG channel α subunit (CNG2) and a β subunit (CNG5), which when heterologously expressed form a channel with properties similar but not identical to those of native olfactory neurons. We have cloned a new type of CNG channel β subunit (CNG4.3) from rat olfactory epithelium. CNG4.3 derives from the same gene as the rod photoreceptor β subunit (CNG4.1) but lacks the long, glutamic acid-rich domain found in the N terminus of CNG4.1. Northern blot and in situ hybridization revealed that CNG4.3 is expressed specifically in olfactory neurons. Expression of CNG4.3 in human embryonic kidney 293 cells did not lead to detectable currents. Coexpression of CNG4.3 with CNG2 induced a current with significantly increased sensitivity for cAMP whereas cGMP affinity was not altered. Additionally, CNG4.3 weakened the outward rectification of the current in the presence of extracellular Ca2+, decreased the relative permeability for Ca2+, and enhanced the sensitivity for l-cis diltiazem. Upon coexpression of CNG2, CNG4.3, and CNG5, a conductance with a cAMP sensitivity greater than that of either the CNG2/CNG4.3 or the CNG2/CNG5 channel and near that of native olfactory channel was observed. Our data suggest that CNG4.3 forms a subunit of the native olfactory CNG channel. The expression of various CNG4 isoforms in retina and olfactory epithelium indicates that the CNG4 subunit may be necessary for normal function of both photoreceptor and olfactory CNG channels.

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The tissue distributions and physiological properties of a variety of cloned voltage-gated potassium channel genes have been characterized extensively, yet relatively little is known about the mechanisms controlling expression of these genes. Here, we report studies on the regulation of Kv1.1 expressed endogenously in the C6 glioma cell line. We demonstrate that elevation of intracellular cAMP leads to the accelerated degradation of Kv1.1 RNA. The cAMP-induced decrease in Kv1.1 RNA is followed by a decrease in Kv1.1 protein and a decrease in the whole cell sustained K+ current amplitude. Dendrotoxin-I, a relatively specific blocker of Kv1.1, blocks 96% of the sustained K+ current in glioma cells, causing a shift in the resting membrane potential from −40 mV to −7 mV. These data suggest that expression of Kv1.1 contributes to setting the resting membrane potential in undifferentiated glioma cells. We therefore suggest that receptor-mediated elevation of cAMP reduces outward K+ current density by acting at the translational level to destabilize Kv1.1 RNA, an additional mechanism for regulating potassium channel gene expression.

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Epithelial Na+ channels are expressed widely in absorptive epithelia such as the renal collecting duct and the colon and play a critical role in fluid and electrolyte homeostasis. Recent studies have shown that these channels interact via PY motifs in the C terminals of their α, β, and γ subunits with the WW domains of the ubiquitin-protein ligase Nedd4. Mutation or deletion of these PY motifs (as occurs, for example, in the heritable form of hypertension known as Liddle’s syndrome) leads to increased Na+ channel activity. Thus, binding of Nedd4 by the PY motifs would appear to be part of a physiological control system for down-regulation of Na+ channel activity. The nature of this control system is, however, unknown. In the present paper, we show that Nedd4 mediates the ubiquitin-dependent down-regulation of Na+ channel activity in response to increased intracellular Na+. We further show that Nedd4 operates downstream of Go in this feedback pathway. We find, however, that Nedd4 is not involved in the feedback control of Na+ channels by intracellular anions. Finally, we show that Nedd4 has no influence on Na+ channel activity when the Na+ and anion feedback systems are inactive. We conclude that Nedd4 normally mediates feedback control of epithelial Na+ channels by intracellular Na+, and we suggest that the increased Na+ channel activity observed in Liddle’s syndrome is attributable to the loss of this regulatory feedback system.

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Traditionally, the structure and properties of natural products have been determined by total synthesis and comparison with authentic samples. We have now applied this procedure to the first nonproteinaceous ion channel, isolated from bacterial plasma membranes, and consisting of a complex of poly(3-hydroxybutyrate) and calcium polyphosphate. To this end, we have now synthesized the 128-mer of hydroxybutanoic acid and prepared a complex with inorganic calcium polyphosphate (average 65-mer), which was incorporated into a planar lipid bilayer of synthetic phospholipids. We herewith present data that demonstrate unambiguously that the completely synthetic complex forms channels that are indistinguishable in their voltage-dependent conductance, in their selectivity for divalent cations, and in their blocking behavior (by La3+) from channels isolated from Escherichia coli. The implications of our finding for prebiotic chemistry, biochemistry, and biology are discussed.

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The reconstituted pea chloroplastic outer envelope protein of 16 kDa (OEP16) forms a slightly cation-selective, high-conductance channel with a conductance of Λ = 1,2 nS (in 1 M KCl). The open probability of OEP16 channel is highest at 0 mV (Popen = 0.8), decreasing exponentially with higher potentials. Transport studies using reconstituted recombinant OEP16 protein show that the OEP16 channel is selective for amino acids but excludes triosephosphates or uncharged sugars. Crosslinking indicates that OEP16 forms a homodimer in the membrane. According to its primary sequence and predicted secondary structure, OEP16 shows neither sequence nor structural homologies to classical porins. The results indicate that the intermembrane space between the two envelope membranes might not be as freely accessible as previously thought.

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We previously reported the presence of a novel variant (β-T594M) of the amiloride-sensitive Na+ channel (ASSC) in which the threonine residue at position 594 in the β-subunit has been replaced by a methionine residue. Electrophysiological studies of the ASSC on Epstein–Barr virus (EBV)-transformed lymphocytes carrying this variant showed that the 8-(4-chlorophenylthio) adenosine 3′:5′-cyclic monophosphate (8cpt-cAMP)-induced responses were enhanced when compared to wild-type EBV-transformed lymphocytes. Furthermore, in wild-type EBV-transformed cells, the 8cpt-cAMP-induced response was totally blocked by the phorbol ester, phorbol 12-myristate 13-acetate (PMA). This inhibitory effect of PMA was blocked by a protein kinase C inhibitor, chelerythrine. We now have identified individuals who are homozygous for this variant, and showed that PMA had no effect on the 8cpt-cAMP-induced responses in the EBV-transformed lymphocytes from such individuals. Cells heterozygous for this variant showed mixed responses to PMA, with the majority of cells partially inhibited by PMA. Our results demonstrate that an alteration in a single amino acid residue in the β-subunit of the ASSC can lead to a total loss of inhibition to PMA, and establish the β-subunit as having an important role in conferring a regulatory effect on the ASSC of lymphocytes.

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Streaming potentials across cloned epithelial Na+ channels (ENaC) incorporated into planar lipid bilayers were measured. We found that the establishment of an osmotic pressure gradient (Δπ) across a channel-containing membrane mimicked the activation effects of a hydrostatic pressure differential (ΔP) on αβγ-rENaC, although with a quantitative difference in the magnitude of the driving forces. Moreover, the imposition of a Δπ negates channel activation by ΔP when the Δπ was directed against ΔP. A streaming potential of 2.0 ± 0.7 mV was measured across αβγ-rat ENaC (rENaC)-containing bilayers at 100 mM symmetrical [Na+] in the presence of a 2 Osmol/kg sucrose gradient. Assuming single file movement of ions and water within the conduction pathway, we conclude that between two and three water molecules are translocated together with a single Na+ ion. A minimal effective pore diameter of 3 Å that could accommodate two water molecules even in single file is in contrast with the 2-Å diameter predicted from the selectivity properties of αβγ-rENaC. The fact that activation of αβγ-rENaC by ΔP can be reproduced by the imposition of Δπ suggests that water movement through the channel is also an important determinant of channel activity.

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Pulmonary neuroepithelial bodies (NEB) are widely distributed throughout the airway mucosa of human and animal lungs. Based on the observation that NEB cells have a candidate oxygen sensor enzyme complex (NADPH oxidase) and an oxygen-sensitive K+ current, it has been suggested that NEB may function as airway chemoreceptors. Here we report that mRNAs for both the hydrogen peroxide sensitive voltage gated potassium channel subunit (KH2O2) KV3.3a and membrane components of NADPH oxidase (gp91phox and p22phox) are coexpressed in the NEB cells of fetal rabbit and neonatal human lungs. Using a microfluorometry and dihydrorhodamine 123 as a probe to assess H2O2 generation, NEB cells exhibited oxidase activity under basal conditions. The oxidase in NEB cells was significantly stimulated by exposure to phorbol esther (0.1 μM) and inhibited by diphenyliodonium (5 μM). Studies using whole-cell voltage clamp showed that the K+ current of cultured fetal rabbit NEB cells exhibited inactivating properties similar to KV3.3a transcripts expressed in Xenopus oocyte model. Exposure of NEB cells to hydrogen peroxide (H2O2, the dismuted by-product of the oxidase) under normoxia resulted in an increase of the outward K+ current indicating that H2O2 could be the transmitter modulating the O2-sensitive K+ channel. Expressed mRNAs or orresponding protein products for the NADPH oxidase membrane cytochrome b as well as mRNA encoding KV3.3a were identified in small cell lung carcinoma cell lines. The studies presented here provide strong evidence for an oxidase-O2 sensitive potassium channel molecular complex operating as an O2 sensor in NEB cells, which function as chemoreceptors in airways and in NEB related tumors. Such a complex may represent an evolutionary conserved biochemical link for a membrane bound O2-signaling mechanism proposed for other cells and life forms.

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A K+ channel gene has been cloned from Drosophila melanogaster by complementation in Saccharomyces cerevisiae cells defective for K+ uptake. Naturally expressed in the neuromuscular tissues of adult flies, this gene confers K+ transport capacity on yeast cells when heterologously expressed. In Xenopus laevis oocytes, expression yields an ungated K+-selective current whose attributes resemble the “leak” conductance thought to mediate the resting potential of vertebrate myelinated neurons but whose molecular nature has long remained elusive. The predicted protein has two pore (P) domains and four membrane-spanning helices and is a member of a newly recognized K+ channel family. Expression of the channel in flies and yeast cells makes feasible studies of structure and in vivo function using genetic approaches that are not possible in higher animals.