The role of visual landmarks in the avian familiar area map - Commentary

The question of whether homing pigeons use visual landmarks for orientation from distant, familiar sites is an unresolved issue in the field of avian navigation. Where evidence has been found, the question still remains as to whether the landmarks are used independent of the map and compass mechanism for orientation that is so important to birds. Recent research has challenged the extent to which experiments that do not directly manipulate the visual sense can be used as evidence for compass-independent orientation. However, it is proposed that extending a new technique for research on vision in homing to include manipulation of the compasses used by birds might be able to resolve this issue. The effect of the structure of the visual sense of the homing pigeon on its use of visual landmarks is also considered.

Further evidence for visual landmark involvement in the pigeon's familiar area map

In previous experiments suggesting that previewing visual landscapes speeds homing from familiar release sites, restricted access to olfactory cues may have artefactually encouraged homing pigeons, Calumba livia, to resort to visual landmark orientation. Since evidence for the role of visual landmarks in wide-ranging avian orientation is still equivocal, Braithwaite & Guilford's (1991, Proc. R. Sec. Lond. Ser. B, 245, 183-186) 'previewing' experiments were replicated: birds were allowed or denied visual access to a familiar site prior to release, but allowed ample access to olfactory cues. In experiment 1, allowing birds to preview familiar sites for 5 min prior to release enhanced homing speeds by about 12%. In experiment 2, modified to reduce between-day effects on variation, previewing enhanced homing speeds by about 16%. These experiments support the conclusion that visual landmarks remote from sight of the loft are an important component of the familiar area map, although the nature of the landmarks and how they are encoded remain to be determined. (C) 1997 The Association for the Study of Animal Behaviour.

Tracking clock-shifted homing pigeons from familiar release sites

Clock-shifted homing pigeons were tracked from familiar sites 17.1km and 23.5 km from the home loft in Pisa, Italy, using an on-board route recorder. At the first release site, north of home, the majority of clock-shifted birds had relatively straight tracks comparable with those of control birds, At the second release site, south of home, the clock-shifted birds deflected in the direction predicted for the degree of clock shift, with many birds travelling some distance in the wrong direction before correcting their course. The possible role of large-scale terrain features in homing pigeon navigation is discussed.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.