A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

Zero momentum gluons and the total pp and pbarp cross-sections

We describe a QCD motivated model for total cross-sections which uses the eikonal representation and incorporates QCD mini-jets to drive the rise with energy of the cross-section, while the impact parameter distribution is obtained through the Fourier transform of the transverse momentum distribution of soft gluons emitted in the parton-parton interactions giving rise to mini-jets in the final state. A singular but integral expression for the running coupling constant in the infrared region is part of this model.

QCD and total cross-sections: photons and hadrons

In this contribution, we discuss a total cross-section model which can be applied to both photon and purely hadronic processes. We find that the model can reproduce photo-production cross-sections, as well as extrapolations of gamma p processes to gamma p using vector meson dominance models, with minimal modifications from the proton case.

Reducing Buffer Requirements in Core Routers using Dynamic Buffering

Earlier studies have exploited statistical multiplexing of flows in the core of the Internet to reduce the buffer requirement in routers. Reducing the memory requirement of routers is important as it enables an improvement in performance and at the same time a decrease in the cost. In this paper, we observe that the links in the core of the Internet are typically over-provisioned and this can be exploited to reduce the buffering requirement in routers. The small on-chip memory of a network processor (NP) can be effectively used to buffer packets during most regimes of traffic. We propose a dynamic buffering strategy which buffers packets in the receive and transmit buffers of a NP when the memory requirement is low. When the buffer requirement increases due to bursts in the traffic, memory is allocated to packets in the off-chip DRAM. This scheme effectively mitigates the DRAM access bottleneck, as only a part of the traffic is stored in the DRAM. We build a Petri net model and evaluate the proposed scheme with core Internet like traffic. At 77% link utilization, the dynamic buffering scheme has a drop rate of just 0.65%, whereas the traditional DRAM buffering has 4.64% packet drop rate. Even with a high link utilization of 90%, which rarely happens in the core, our dynamic buffering results in a packet drop rate of only 2.17%, while supporting a throughput of 7.39 Gbps. We study the proposed scheme under different conditions to understand the provisioning of processing threads and to determine the queue length at which packets must be buffered in the DRAM. We show that the proposed dynamic buffering strategy drastically reduces the buffering requirement while still maintaining low packet drop rates.

Total Factor Productivity Growth and Output Growth in Indian Electronics Industry in the Liberalization Era: An Empirical Examination

This paper analyses the efficiency and productivity growth of Electronics industry, which is considered one of the vibrant and rapidly growing manufacturing industry sub-sectors of India in the liberalization era since 1991. The main objective of the paper is to examine the extent and growth of Total Factor Productivity (TFP) and its components namely, Technical Efficiency Change (TEC) and Technological Progress (TP) and its contribution to total output growth. In this study, the electronics industry is broadly classified into communication equipments, computer hardware, consumer electronics and other electronics, with the purpose of performing a comparative analysis of productivity growth for each of these sub-sectors for the time period 1993-2004. The paper found that the sub-sectors have improved in terms of economies of scale and contribution of capital.The change in technical efficiency and technological progress moved in reverse directions. Three of the four industry witnessed growth in the output primarily due to TFPG and the contribution of input growth to output growth had been negative/negligible, except for Computer hardware where contribution from both input growth and TFPG to output growth were prominent. The paper explored the possible reasons that addressed the issue of low technical efficiency and technological progress in the industry.

Total synthesis of panaxytriol and panaxydiol

The enantioselective total synthesis of the diyne containing natural products panaxytriol and (3S,10R)-panaxydiol from L-tartaric acid is reported. Key steps in the synthesis include the elaboration of a gamma-hydroxy amide derived from tartaric acid to the required alkyne and the formation of the desired diyne unit by a Cadiot-Chodkiewicz coupling. (C) 2011 Elsevier Ltd. All rights reserved.

Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.

Total synthesis of (-)-ent-pachastrissamine (ent-Jaspine B)

The total synthesis of the enantiomer of the tetrahydrofuran containing natural product Jaspine B is reported. The key reactions in the synthesis include formation of the tetrahydrofuran unit by an acid mediated Williamson etherification and a subsequent elaboration with an olefin cross metathesis reaction. (C) 2011 Elsevier Ltd. All rights reserved.

Operational experience on a grid connected 100 kWe biomass gasification power plant in Karnataka, India

The paper reports the operational experience from a 100 kWe gasification power plant connected to the grid in Karnataka. Biomass Energy for Rural India (BERI) is a program that implemented gasification based power generation with an installed capacity of 0.88 MWe distributed over three locations to meet the electrical energy needs in the district of Tumkur. The operation of one 100 kWe power plant was found unsatisfactory and not meeting the designed performance. The Indian Institute of Science, Bangalore, the technology developer, took the initiative to ensure the system operation, capacity building and prove the designed performance. The power plant connected to the grid consists of the IISc gasification system which includes reactor, cooling, cleaning system, fuel drier and water treatment system to meet the producer gas quality for an engine. The producer gas is used as a fuel in Cummins India Limited, GTA 855 G model, turbo charged engine and the power output is connected to the grid. The system has operated for over 1000 continuous hours, with only about 70 h of grid outages. The total biomass consumption for 1035 h of operation was 111 t at an average of 107 kg/h. Total energy generated was 80.6 MWh reducing over loot of CO(2) emissions. The overall specific fuel consumption was about 1.36 kg/kWh, amounting to an overall efficiency from biomass to electricity of about 18%. The present operations indicate that a maintenance schedule for the plant can be at the end of 1000 h. The results for another 1000 h of operation by the local team are also presented. (C) 2011 International Energy Initiative. Published by Elsevier Inc. All rights reserved.

Total Factor Productivity in Indian Electronic Sector after Liberalisation: Sources and Outcomes

This paper analyses the efficiency and productivity growth of the Electronic Sector of India in the liberalization era since 1991. The study gives an insight into the process of the growth of one of the most upcoming sector of this decade. This sector has experienced a vast structural change along with the changing economic structures in India after liberalisation. With the opening up of this sector to foreign market and incoming of multinational companies, the environment has become highly competitive. The law that operates is that of Darwin’s ‘Survival of the fittest’. Existing industries experience a continuous threat of exit due to entrance of new potential entrants. Thus, it becomes inevitable for the existing industries in this sector to improve productivity growth for their survival. It is thus important to analyze how the industries in this sector have performed over the years and what are the factors that have contributed to the overall output growth.

Total and inelastic cross sections at LHC at root s=7 TeV and beyond

We discuss expectations for the total and inelastic cross sections at LHC CM energies root s = 7 TeV and 14 TeV obtained in an eikonal minijet model augmented by soft gluon k(t)-resummation, which we describe in some detail. We present a band of predictions which encompass recent LHC data and suggest that the inelastic cross section described by two-channel eikonal models include only uncorrelated processes. We show that this interpretation of the model is supported by the LHC data.