Nearshore oscillating wave surge converters and the development of Oyster

Oscillating wave surge converters (OWSCs) are a class of wave power technology that exploits the enhanced horizontal fluid particle movement of waves in the nearshore coastal zone with water depths of 10–20 m. OWSCs predominantly oscillate horizontally in surge as opposed to the majority of wave devices, which oscillate vertically in heave and usually are deployed in deeper water. The characteristics of the nearshore wave resource are described along with the hydrodynamics of OWSCs. The variables in the OWSC design space are discussed together with a presentation of some of their effects on capture width, frequency bandwidth response and power take-off characteristics. There are notable differences between the different OWSCs under development worldwide, and these are highlighted. The final section of the paper describes Aquamarine Power’s 315kW Oyster 1 prototype, which was deployed at the European Marine Energy Centre in August 2009. Its place in the OWSC design space is described along with the practical experience gained. This has led to the design of Oyster 2, which was deployed in August 2011. It is concluded that nearshore OWSCs are serious contenders in the mix of wave power technologies. The nearshore wave climate has a narrower directional spread than the offshore, the largest waves are filtered out and the exploitable resource is typically only 10–20% less in 10m depth compared with 50m depth. Regarding the devices, a key conclusion is that OWSCs such as Oyster primarily respond in the working frequency range to the horizontal fluid acceleration; Oyster is not a drag device responding to horizontal fluid velocity. The hydrodynamics of Oyster is dominated by inertia with added inertia being a very significant contributor. It is unlikely that individual flap modules will exceed 1MW in installed capacity owing to wave resource, hydrodynamic and economic constraints. Generating stations will be made up of line arrays of flaps with communal secondary power conversion every 5–10 units.

The opportunities and limitations of using CFD in the development of wave energy converters

Most Wave Energy Converters (WECs) being developed are fundamentally different from known marine structures. Limited experience is a fundamental challenge for the design, especially issues concerning load assumptions and power estimates. Reynolds-Averaged Navier-Stokes (RANS) CFD methods are being used successfully in many areas of marine engineering. They have been shown to accurately simulate many hydrodynamic effects and are a helpful tool for investigating complex flows. The major drawback is the significant computational power required and the associated overhead with pre and post-processing. This paper presents the challenges and advantages in the application of RANS CFD methods in the design process of a wave energy converter and compares the time, labour and ultimately financial requirements for obtaining practical results.

Power take-off and damping of an oscillating wave surge converter

The European Union has set a target of 20% for the share of renewable energy sources in gross final energy consumption in 2020. These renewable energy targets are priority objectives for the Europe 2020 strategy for inclusive growth. In line with the European Union renewable energy policies, the Northern Ireland Executive has a target to deliver 40% renewable electricity by 2020. Currently, Northern Ireland imports 98% of the energy it uses in the form of fossil fuels. Locally produced energy and electricity is needed to ensure sustainable development. The aim of this research is to develop part of a strategy for the mechanical power take-off system for a flap type wave energy converter. Aquamarine Power Ltd’s Oyster flap was the device used for simulation and testing purposes. In this paper the state-of-the-art of wave energy converters is reviewed and a 40th scale test model was developed and built.

The hydrodynamics of small seabed mounted bottom hinged wave energy converters in shallow water:PhD thesis

This thesis investigates the hydrodynamics of a small, seabed mounted, bottom hinged, wave energy converter in shallow water. The Oscillating Wave Surge Converter is a pitching flap-type device which is located in 10-15m of water to take advantage of the amplification of horizontal water particle motion in shallow water. A conceptual model of the hydrodynamics of the device has been formulated and shows that, as the motion of the flap is highly constrained, the magnitude of the force applied to the flap by the wave is strongly linked to the power absorption.

An extensive set of experiments has been carried out in the wave tank at Queen’s University at both 40th and 20th scales. The experiments have included testing in realistic sea states to estimate device performance as well as fundamental tests using small amplitude monochromatic waves to determine the force applied to the flap by the waves. The results from the physical modelling programme have been used in conjunction with numerical data from WAMIT to validate the conceptual model.

The work finds that tuning the OWSC to the incident wave periods is problematic and only results in a marginal increase in power capture. It is also found that the addition of larger diameter rounds to the edges of the flap reduces viscous losses and has a greater effect on the performance of the device than tuning. As wave force is the primary driver of device performance it is shown that the flap should fill the water column and should pierce the water surface to reduce losses due to wave overtopping.

With the water depth fixed at approximately 10m it is shown that the width of the flap has the greatest impact on the magnitude of wave force, and thus device performance. An 18m wide flap is shown to have twice the absorption efficiency of a 6m wide flap and captures 6 times the power. However, the increase in power capture with device width is not limitless and a 24m wide flap is found to be affected by two-dimensional hydrodynamics which reduces its performance per unit width, especially in sea states with short periods. It is also shown that as the width increases the performance gains associated with the addition of the end effectors reduces. Furthermore, it is shown that as the flap width increases the natural pitching period of the flap increases, thus detuning the flap further from the wave periods of interest for wave energy conversion.

The effect of waves approaching the flap from an oblique angle is also investigated and the power capture is found to decrease with the cosine squared of the encounter angle. The characteristic of the damping applied by the power take off system is found to have a significant effect on the power capture of the device, with constant damping producing between 20% and 30% less power than quadratic damping. Furthermore, it is found that applying a higher level of damping, or a damping bias, to the flap as it pitches towards the beach increases the power capture by 10%.

A further set of experiments has been undertaken in a case study used to predict the power capture of a prototype of the OWSC concept. The device, called the Oyster Demonstrator, has been developed by Aquamarine Power Ltd. and is to be installed at the European Marine Energy Centre, Scotland, in 2009.

The work concludes that OWSC is a viable wave energy converter and absorption efficiencies of up 75% have been measured. It is found that to maximise power absorption the flap should be approximately 20m wide with large diameter rounded edges, having its pivot close to the seabed and its top edge piercing the water surface.

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory
access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement
the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to
67.1%, under a power cap.

Inter-Area Power Oscillation Frequency Mode with Wind Turbine Generator in Irish Power System using PMU Data

Two case studies are presented in this paper to demonstrate the impact of different power system operation conditions on the power oscillation frequency modes in the Irish power system. A simplified 2 area equivalent of the Irish power system has been used in this paper, where area 1 represents the Republic of Ireland power system and area 2 represents the Northern Ireland power system.

The potential power oscillation frequency modes on the interconnector during different operation conditions have been analysed in this paper. The main objective of this paper is to analyse the influence of different operation conditions involving wind turbine generator (WTG) penetration on power oscillation frequency modes using phasor measurement unit (PMU) data.

Fast Fourier transform (FFT) analysis was performed to identify the frequency oscillation mode while correlation coefficient analysis was used to determine the source of the frequency oscillation. The results show that WTG, particularly fixed speed induction generation (FSIG), gives significant contribution to inter-area power oscillation frequency modes during high WTG operation.

An optimal algorithm for low power multiplierless FIR filter design using chebychev criterion

In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.

Idealized Operation of Third-Harmonic-Peaking Class-Ef Power Amplifier with Extended Maximum Operating Frequency

A new variant of Class-EF power amplifier (PA), the so-called third-harmonic-peaking Class-EF, is presented. It inherits a soft-switching operation from the Class-E PA and a low peak switch voltage from the Class-F PA. More importantly, the new topology allows operations at higher frequencies and permits deployment of large transistors which is normally prohibited since they are always accompanied with high output capacitances. Using a simple transmission-line load network, the PA is synthesized to satisfy Class-EF impedances at fundamental frequency, third harmonic, and all even harmonics as well as to simultaneously provide an impedance matching to 50-Ω load.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

Secure D2D Communication in Large-Scale Cognitive Cellular Networks with Wireless Power Transfer

In this paper, we investigate secure device-to-device (D2D) communication in energy harvesting large-scale cognitive cellular networks. The energy constrained D2D transmitter harvests energy from multi-antenna equipped power beacons (PBs), and communicates with the corresponding receiver using the spectrum of the cellular base stations (BSs). We introduce a power transfer model and an information signal model to enable wireless energy harvesting and secure information transmission. In the power transfer model, we propose a new power transfer policy, namely, best power beacon (BPB) power transfer. To characterize the power transfer reliability of the proposed policy, we derive new closed-form expressions for the exact power outage probability and the asymptotic power outage probability with large antenna arrays at PBs. In the information signal model, we present a new comparative framework with two receiver selection schemes: 1) best receiver selection (BRS), and 2) nearest receiver selection (NRS). To assess the secrecy performance, we derive new expressions for the secrecy throughput considering the two receiver selection schemes using the BPB power transfer policies. We show that secrecy performance improves with increasing densities of PBs and D2D receivers because of a larger multiuser diversity gain. A pivotal conclusion is reached that BRS achieves better secrecy performance than NRS but demands more instantaneous feedback and overhead.

Small Signal Stability Performance of Power System during High Penetration of Wind Generation

The small signal stability of interconnected power systems is one of the important aspects that need to be investigated since the oscillations caused by this kind of instability have caused many incidents. With the increasing penetration of wind power in the power system, particularly doubly fed induction generator (DFIG), the impact on the power system small signal stability performance should be fully investigated. Because the DFIG wind turbine integration is through a fast action converter and associated control, it does not inherently participate in the electromechanical small signal oscillation. However, it influences the small signal stability by impacting active power flow paths in the network and replacing synchronous generators that have power system stabilizer (PSS). In this paper, the IEEE 39 bus test system has been used in the analysis. Furthermore, four study cases and several operation scenarios have been conducted and analysed. The selective eigenvalue Arnoldi/lanczos's method is used to obtain the system eigenvalue in the range of frequency from 0.2 Hz to 2 Hz which is related to electromechanical oscillations. Results show that the integration of DFIG wind turbines in a system during several study cases and operation scenarios give different influence on small signal stability performance.

New multi-stage DC-DC converters for grid-connected photovoltaic systems

Renewable energy is high on international and national agendas. Currently, grid-connected photovoltaic (PV) systems are a popular technology to convert solar energy into electricity. Existing PV panels have a relatively low and varying output voltage so that the converter installed between the PVs and the grid should be equipped with high step-up and versatile control capabilities. In addition, the output current of PV systems is rich in harmonics which affect the power quality of the grid. In this paper, a new multi-stage hysteresis control of a step-up DC-DC converter is proposed for integrating PVs into a single-phase power grid. The proposed circuitry and control method is experimentally validated by testing on a 600W prototype converter. The developed technology has significant economic implications and could be applied to many distributed generation (DG) systems, especially for the developing countries which have a large number of small PVs connected to their single-phase distribution network. 

New SR drive with integrated charging capacity for plug-in hybrid electric vehicles (PHEVs)

Plug-in hybrid electric vehicles (PHEVs) provide much promise in reducing greenhouse gas emissions and, thus, are a focal point of research and development. Existing on-board charging capacity is effective but requires the use of several power conversion devices and power converters, which reduce reliability and cost efficiency. This paper presents a novel three-phase switched reluctance (SR) motor drive with integrated charging functions (including internal combustion engine and grid charging). The electrical energy flow within the drivetrain is controlled by a power electronic converter with less power switching devices and magnetic devices. It allows the desired energy conversion between the engine generator, the battery, and the SR motor under different operation modes. Battery-charging techniques are developed to operate under both motor-driving mode and standstill-charging mode. During the magnetization mode, the machine's phase windings are energized by the dc-link voltage. The power converter and the machine phase windings are controlled with a three-phase relay to enable the use of the ac-dc rectifier. The power converter can work as a buck-boost-type or a buck-type dc-dc converter for charging the battery. Simulation results in MATLAB/Simulink and experiments on a 3-kW SR motor validate the effectiveness of the proposed technologies, which may have significant economic implications and improve the PHEVs' market acceptance