A Coalitional Game Framework for Cooperative Secondary Spectrum Access

We consider a framework in which several service providers offer downlink wireless data access service in a certain area. Each provider serves its end-users through opportunistic secondary spectrum access of licensed spectrum, and needs to pay primary license holders of the spectrum usage based and membership based charges for such secondary spectrum access. In these circumstances, if providers pool their resources and allow end-users to be served by any of the cooperating providers, the total user satisfaction as well as the aggregate revenue earned by providers may increase. We use coalitional game theory to investigate such cooperation among providers, and show that the optimal cooperation schemes can be obtained as solutions of convex optimizations. We next show that under usage based charging scheme, if all providers cooperate, there always exists an operating point that maximizes the aggregate revenue of providers, while presenting each provider a share of the revenue such that no subset of providers has an incentive to leave the coalition. Furthermore, such an operating point can be computed in polynomial time. Finally, we show that when the charging scheme involves membership based charges, the above result holds in important special cases.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Explorations en route to synthesis of tashironins: singlet oxygen cycloaddition to 1,3-cyclopentadienes embedded within allo-cedrane framework

In an approach directed toward a tashironin based complex natural product, efficacy of the singlet oxygen mediated [4+2]-cycloaddition to a tetracyclic cyclopentadiene has been evaluated to install the key cis-1,4-dihydroxy functionality. (C) 2011 Elsevier Ltd. All rights reserved.

GEMS of SAPPhIRE: A Framework for Designing?

This paper proposes a framework of designing for conceptual and early embodiment design that uses physical laws and effects explicitly as a central aspect for designing. This is especially important in domains that make explicit use of physical laws and effects in their design, such as novel sensors. The objectives of the paper are: (a) Develop a model, (b) Empirically evaluate the model and (c) Propose a framework. The model is developed by integrating the activity- and outcome-based elements. The model is validated empirically by analyzing protocols of design sessions to find instances of activities and outcomes. Based on the findings, a framework is proposed on how designing should be done. Elements of GEMS (Generate-Evaluate-Modify-Select) and SAPPhIRE (State change-Action-Part-Phenomenon-Input-oRgan-Effect) are used for developing the model.Empirical evaluation confirms that designing can be modeled with the activity and outcome elements. The paper concludes with the identification of areas that require support and future work.

Fluorescent metal-organic framework for selective sensing of nitroaromatic explosives

Highly luminescent micrometre-sized fine particles of a Zn(II) metal-organic framework (MOF) of a new pi-electron rich tricarboxylate dispersed in ethanol is demonstrated as a selective sensory material for the detection of nitroaromatic explosives via a fluorescence quenching mechanism.

An eight-connected metal organic framework based on Cu(5) clusters: Synthesis, structure, magnetic and catalytic properties

A reaction of copper acetate, 5-nitroisophthalic acid in a water-methanol mixture under solvothermal condition results in a new metal-organic framework compound, [Cu(5)(mu(3)-OH)(2)(H(2)O)(6){(NO(2))-C(6)H(3)-(COO)(2)}(4)]center dot 5H(2)O, (1). The compound contains Cu5 pentameric cluster units connected by 5-nitro isophthalate (NIPA) moieties forming a CdCl(2)-like layer, which are further connected by another NIPA moiety forming the three-dimensional structure. The water molecules in (1) can be reversibly adsorbed. The removal of water accompanies a change in the colour as well as a structural re-organization. Magnetic studies suggest strong antiferromagnetie correlations between the Cu5 cluster units. The compound (1) exhibits heterogeneous Lewis acid catalysis for the cyanosilylation of imines with more than 95 % selectivity. Compound (1) has been characterized by IR, UV-vis, TGA, powder XRD studies.

H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions

The success of an ABV IP depends highly on the associated debugging environment. An efficient debugging environment helps the user to find out the exact location of the failure. Moreover, it provides information to the user in a refined detail of abstraction and permit adequate interaction. It has also been realized that adequate visualization support helps in tracking the behavioral aspects of the Design Under Test (DUT). Currently, the debugging tools provide information in the signal level and do not provide any information about the high-level behavior of the DUT. We present a debugging framework that takes the design specification, assertions and the user intent in a simple format and provides detailed information by processing the design trace on-line, or off-line. We also present a visualization framework to ease the debugging procedure. We have experimented with industrial standard on-chip bus protocols that ensure that this utility can be incorporated successfully in the present functional verification flow.