Predictive control for spacecraft rendezvous in an elliptical orbit using an FPGA

A field programmable gate array (FPGA)-based predictive controller for a spacecraft rendezvous manoeuvre is presented. A linear time varying prediction model is used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of manoeuvres. The resulting constrained optimisation problems are solved using a primal dual interior point algorithm. The majority of the computational demand is in solving a set of linear equations at each iteration of this algorithm. To accelerate this operation, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft core processor. The system is demonstrated in closed loop by linking the FPGA with a simulation of the plant dynamics running in Simulink on a PC, using Ethernet. © 2013 EUCA.

Progress in the understanding of Ni silicide formation for advanced MOS structures

Metallic silicides have been used as contact materials on source/drain and gate in metal-oxide semiconductor (MOS) structure for 40 years. Since the 65 nm technology node, NiSi is the preferred material for contact in microelectronic due to low resistivity, low thermal budget, and low Si consumption. Ni(Pt)Si with 10 at.% Pt is currently employed in recent technologies since Pt allows to stabilize NiSi at high temperature. The presence of Pt and the very low thickness (<10 nm) needed for the device contacts bring new concerns for actual devices. In this work, in situ techniques [X-ray diffraction (XRD), X-ray reflectivity (XRR), sheet resistance, differential scanning calorimetry (DSC)] were combined with atom probe tomography (APT) to study the formation mechanisms as well as the redistribution of dopants and alloy elements (Pt, Pd.) during the silicide formation. Phenomena like nucleation, lateral growth, interfacial reaction, diffusion, precipitation, and transient phase formation are investigated. The effect of alloy elements (Pt, Pd.) and dopants (As, B.) as well as stress and defects induced by the confinement in devices on the silicide formation mechanism and alloying element redistribution is examined. In particular APT has been performed for the three-dimensional (3D) analysis of MOSFET at the atomic scale. The advances in the understanding of the mechanisms of formation and redistribution are discussed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Articulating current service development practices: a qualitative analysis of eleven mental health projects.

BACKGROUND: The utilisation of good design practices in the development of complex health services is essential to improving quality. Healthcare organisations, however, are often seriously out of step with modern design thinking and practice. As a starting point to encourage the uptake of good design practices, it is important to understand the context of their intended use. This study aims to do that by articulating current health service development practices. METHODS: Eleven service development projects carried out in a large mental health service were investigated through in-depth interviews with six operation managers. The critical decision method in conjunction with diagrammatic elicitation was used to capture descriptions of these projects. Stage-gate design models were then formed to visually articulate, classify and characterise different service development practices. RESULTS: Projects were grouped into three categories according to design process patterns: new service introduction and service integration; service improvement; service closure. Three common design stages: problem exploration, idea generation and solution evaluation - were then compared across the design process patterns. Consistent across projects were a top-down, policy-driven approach to exploration, underexploited idea generation and implementation-based evaluation. CONCLUSIONS: This study provides insight into where and how good design practices can contribute to the improvement of current service development practices. Specifically, the following suggestions for future service development practices are made: genuine user needs analysis for exploration; divergent thinking and innovative culture for idea generation; and fail-safe evaluation prior to implementation. Better training for managers through partnership working with design experts and researchers could be beneficial.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s. © 2014 AIP Publishing LLC.

High performance bilayer-graphene Terahertz detectors

© 2014 AIP Publishing LLC. We report bilayer-graphene field effect transistors operating as Terahertz (THz) broadband photodetectors based on plasma-waves excitation. By employing wide-gate geometries or buried gate configurations, we achieve a responsivity ∼1.2 V/W (1.3 mA/W) and a noise equivalent power ∼2 × 10-9 W/√Hz in the 0.29-0.38 THz range, in photovoltage and photocurrent mode. The potential of this technology for scalability to higher frequencies and the development of flexible devices makes our approach competitive for a future generation of THz detection systems.

Highly electron transparent Graphene for field emission triode gates

The enhanced emission performance of a graphene/Mo hybrid gate electrode integrated into a nanocarbon field emission micro-triode electron source is presented. Highly electron transparent gate electrodes are fabricated from chemical vapor deposited bilayer graphene transferred to Mo grids with experimental and simulated data, showing that liberated electrons efficiently traverse multi-layer graphene membranes with transparencies in excess of 50-68%. The graphene hybrid gates are shown to reduce the gate driving voltage by 1.1 kV, whilst increasing the electron transmission efficiency of the gate electrode significantly. Integrated intensity maps show that the electron beam angular dispersion is dramatically improved (87.9°) coupled with a 63% reduction in beam diameter. Impressive temporal stability is noted (<1.0%) with surprising negligible long-term damage to the graphene. A 34% increase in triode perveance and an amplification factor 7.6 times that of conventional refractory metal grid gate electrode-based triodes are noted, thus demonstrating the excellent stability and suitability of graphene gates in micro-triode electron sources. A nanocarbon field emission triode with a hybrid gate electrode is developed. The graphene/Mo gate shows a high electron transparency (50-68%) which results in a reduced turn-on potential, increased beam collimation, reduced beam diameter (63%), enhanced stability (<1% variation), a 34% increase in perveance, and an amplification 7.6 times that of equivalent conventional refractory metal gate triodes. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Atom probe tomography of SRAM transistors: Specimen preparation methods and analysis

Different FIB-based sample preparation methods for atom probe analysis of transistors have been proposed and discussed. A special procedure, involving device deprocessing, has been used to analyze by APT a sub-30 nm transistor extracted from a SRAM device. The analysis provides three dimensional compositions of Ni-silicide contact, metal gate and high-k oxide of the transistor gate. © 2013 Elsevier B.V. All rights reserved.

Pt redistribution in N-MOS transistors during Ni salicide process

Atom probe tomography was used to study the redistribution of platinum during Ni(10 at.%Pt) silicidation of n-doped polycrystalline Si. These measurements were performed after the two annealing steps of standard salicide process both on a field-effect transistor and on unpatterned region submitted to the same process. Very similar results are obtained in unpatterned region and in transistor gate contact. The first phase to form is not the expected δ-Ni2Si but the non stoichiometric θ-Ni2Si. Pt redistribution is strongly influenced by this phase and the final distribution is different from what is reported in literature. © 2013 Elsevier B.V. All rights reserved.

Amorphous oxide semiconductor TFTs for displays and imaging

© 2013 IEEE. This paper reviews the mechanisms underlying visible light detection based on phototransistors fabricated using amorphous oxide semiconductor technology. Although this family of materials is perceived to be optically transparent, the presence of oxygen deficiency defects, such as vacancies, located at subgap states, and their ionization under illumination, gives rise to absorption of blue and green photons. At higher energies, we have the usual band-to-band absorption. In particular, the oxygen defects remain ionized even after illumination ceases, leading to persistent photoconductivity, which can limit the frame-rate of active matrix imaging arrays. However, the persistence in photoconductivity can be overcome through deployment of a gate pulsing scheme enabling realistic frame rates for advanced applications such as sensor-embedded display for touch-free interaction.

Top down scale-up of semiconducting nanostructures for large area electronics

In this paper, we present a study on electrical and optical characteristics of n-type tin-oxide nanowires integrated based on top-down scale-up strategy. Through a combination of contact printing and plasma based back-channel passivation, we have achieved stable electrical characteristics with standard deviation in mobility and threshold voltage of 9.1% and 25%, respectively, for a large area of 1× 1 cm2 area. Through use of contact printing, high alignment of nanowires was achieved thus minimizing the number of nanowire-nanowire junctions, which serve to limit carrier transport in the channel. In addition, persistent photoconductivity has been observed, which we attribute to oxygen vacancy ionization and subsequent elimination using a gate pulse driving scheme. © 2014 IEEE.

Study of high performance re-timing using a 40 Gb/s hybrid-integrated mach-zehnder all-optical regenerator

We experimentally show that a hybrid-integrated Mach-Zehnder switch with a high performance gate profile allows retiming of optical signals with an accuracy of 500-700fs even if the input timing jitter is increased to 3ps. © 2004 Optical Society of America.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.

Atom probe tomography for advanced metallization

In microelectronics, the increase in complexity and the reduction of devices dimensions make essential the development of new characterization tools and methodologies. Indeed advanced characterization methods with very high spatial resolution are needed to analyze the redistribution at the nanoscale in devices and interconnections. The atom probe tomography has become an essential analysis to study materials at the nanometer scale. This instrument is the only analytical microscope capable to produce 3D maps of the distribution of the chemical species with an atomic resolution inside a material. This technique has benefit from several instrumental improvements during last years. In particular, the use of laser for the analysis of semiconductors and insulating materials offers new perspectives for characterization. The capability of APT to map out elements at the atomic scale with high sensitivity in devices meets the characterization requirements of semiconductor devices such as the determination of elemental distributions for each device region. In this paper, several examples will show how APT can be used to characterize and understand materials and process for advanced metallization. The possibilities and performances of APT (chemical analysis of all the elements, atomic resolution, planes determination, crystallographic information...) will be described as well as some of its limitations (sample preparation, complex evaporation, detection limit, ...). The examples illustrate different aspect of metallization: dopant profiling and clustering, metallic impurities segregation on dislocation, silicide formation and alloying, high K/metal gate optimization, SiGe quantum dots, as well as analysis of transistors and nanowires. © 2013 Elsevier B.V. All rights reserved.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.