Dual gate photo-thin film transistor with high photoconductive gain for high reliability, and low noise flat panel transparent imager

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency. © 2011 IEEE.

Point injection in trench insulated gate bipolar transistor for ultra low losses

In this paper we propose novel designs that enhance the plasma concentration across the Field Stop IGBT. The "p-ring" and the "point-injection" type devices exhibit increased cathode side conductivity modulation which results in impressive IGBT performance improvement. These designs are shown to be extremely effective in lowering the on-state losses without compromising the switching performance or the breakdown rating. For the same switching losses we can achieve more than 20% reduction of the on state energy losses compared to the conventional FS IGBT. © 2012 IEEE.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Three dimensional distributions of arsenic and platinum within NiSi contact and gate of an n-type transistor

Atom probe tomography was used to study the redistribution of platinum and arsenic atoms after Ni(Pt) silicidation of As-doped polycrystalline Si. These measurements were performed on a field-effect transistor and compared with those obtained in unpatterned region submitted to the same process. These results suggest that Pt and As redistribution during silicide formation is only marginally influenced by the confinement in microelectronic devices. On the contrary, there is a clear difference with the redistribution reported in the literature for the blanket wafers. Selective etching used to remove the non-reacted Ni(Pt) film after the first rapid heat treatment may induce this difference. © 2011 American Institute of Physics.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

AlGaN/AlN/GaN/SiC HEMT structure with high mobility GaN thin layer as channel grown by MOCVD

Enhancement of the electrical properties in an AlGaN/GaN high electron mobility transistor (HEMT) structures was demonstrated by employing the combination of a high mobility GaN channel layer and an AlN interlayer. The structures were grown on 50 mm semi-insulating (SI) 6H-SiC substrates by metalorganic chemical vapor deposition (MOCVD). The room temperature (RT) two-dimensional electron gas (2DEG) mobility was as high as 2215 cm(2)/V s, with a 2DEG concentration of 1.044 x 10(13)cm(-2). The 50 mm HEMT wafer exhibited a low average sheet resistance of 251.0 Omega/square, with a resistance uniformity of 2.02%. The 0.35 Pin gate length HEMT devices based on this material structure, exhibited a maximum drain current density of 1300 mA/mm, a maximum extrinsic transconductance of 314 mS/mm, a current gain cut-off frequency of 28 GHz and a maximum oscillation frequency of 60 GHz. The maximum output power density of 4.10 W/mm was achieved at 8 GHz, with a power gain of 6.13 dB and a power added efficiency (PAE) of 33.6%. (c) 2006 Elsevier B.V. All rights reserved.

Semiconductor optical amplifier optical gate with graded strained bulk-like active structure

A novel semiconductor optical amplifier (SOA) optical gate with a graded strained bulk-like active structure is proposed. A fiber-to-fiber gain of 10 dB when the coupling loss reaches 7 dB/factet and a polarization insensitivity of less than 0.9 dB for multiwavelength and different power input signals over the whole operation current are obtained. Moreover, for our SOA optical gate, a no-loss current of 50 to 70 mA and an extinction ratio of more than 50 dB are realized when the injection current is more than no-loss current, and the maximum extinction ratio reaches 71 dB, which is critical for crosstalk suppression. (C) 2003 society of Photo-Optical Instrumentation Engineers.

MOCVD-Grown AlGaN/AlN/GaN HEMT Structure with High Mobility GaN Thin Layer as Channel on SiC

AlGaN/AlN/GaN high electron mobility transistor (HEMT) structures with a high-mobility GaN thin layer as a channel are grown on high resistive 6H-SiC substrates by metalorganic chemical vapor deposition. The HEMT structure exhibits a typical two-dimensional electron gas (2DEG) mobility of 1944cm2/(V · s) at room temperature and 11588cm2/(V· s) at 80K with almost equal 2DEG concentrations of about 1.03 × 1013 cm-2 High crystal quality of the HEMT structures is confirmed by triple-crystal X-ray diffraction analysis. Atomic force microscopy measurements reveal a smooth AlGaN surface with a root-mean-square roughness of 0. 27nm for a scan area of 10μm × 10μm. HEMT devices with 0.8μm gate length and 1.2mm gate width are fabricated using the structures. A maximum drain current density of 957mA/mm and an extrinsic transconductance of 267mS/mm are obtained.

Observation of N-Shaped Negative Differential Resistance in GaAs-Based Modulation-Doped Field Effect Transistor with InAs Quantum Dots

N-shaped negative differential resistance (NDR) with a high peak-to-valley ratio (PVR) is observed in a GaAs-based modulation-doped field effect transistor (MODFET) with InAs quantum dots (QDs) in the barrier layer (QDFET) compared with a GaAs MODFET. The NDR is explained as the real-space transfer (RST) of high-mobility electrons in a channel into nearby barrier layers with low mobility, and the PVR is enhanced dramatically upon inserting the QD layer. It is also revealed that the QD layer traps holes and acts as a positively charged nano-floating gate after a brief optical illumination, while it acts as a negatively charged nano-floating gate and depletes the adjacent channel when charged by the electrons. The NDR suggests a promising application in memory or high-speed logic devices for the QDFET structure.

Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate

Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.