Novel transparent and flexible transistors for radiation harsh environment

La scoperta dei semiconduttori amorfi ha segnato l’era della microelettronica su larga scala rendendo possibile il loro impiego nelle celle solari o nei display a matrice attiva. Infatti, mentre i semiconduttori a cristalli singoli non sono consoni a questo tipo di applicazioni e i s. policristallini presentano il problema dei bordi di grano, i film amorfi possono essere creati su larga scala (>1 m^2) a basse temperature (ad es. <400 °C) ottenendo performance soddisfacenti sia su substrati rigidi che flessibili. Di recente la ricerca sta compiendo un grande sforzo per estendere l’utilizzo di questa nuova elettronica flessibile e su larga scala ad ambienti soggetti a radiazioni ionizzanti, come lo sono i detector di radiazioni o l’elettronica usata in applicazioni spaziali (satelliti). A questa ricerca volge anche la mia tesi, che si confronta con la fabbricazione e la caratterizzazione di transistor a film sottili basati su ossidi semiconduttori ad alta mobilità e lo studio della loro resistenza ai raggi X. La micro-fabbricazione, ottimizzazione e caratterizzazione dei dispositivi è stata realizzata nei laboratori CENIMAT e CEMOP dell’Università Nova di Lisbona durante quattro mesi di permanenza. Tutti i dispositivi sono stati creati con un canale n di ossido di Indio-Gallio-Zinco (IGZO). Durante questo periodo è stato realizzato un dispositivo dalle ottime performance e con interessanti caratteristiche, una delle quali è la non variazione del comportamento capacitivo in funzione della frequenza e la formidabile resistenza alle radiazioni. Questo dispositivo presenta 114 nm di dielettrico, realizzato con sette strati alternati di SiO2/ Ta2O5. L’attività di ricerca svolta al Dipartimento di Fisica e Astronomia di Bologna riguarda prevalentemente lo studio degli effetti delle radiazioni ionizzanti su TFTs. Gli esperimenti hanno rivelato che i dispositivi godono di una buona stabilità anche se soggetti alle radiazioni. Infatti hanno mostrato performance pressoché inalterate anche dopo un’esposizione a 1 kGy di dose cumulativa di raggi X mantenendo circa costanti parametri fondamentali come la mobilità, il threshold voltage e la sub-threshold slope. Inoltre gli effetti dei raggi X sui dispositivi, così come parametri fondamentali quali la mobilità, si sono rivelati essere notevolmente influenzati dallo spessore del dielettrico.

STOCHASTIC CHARGE TRANSPORT IN MULTI-ISLAND SINGLE-ELECTRON TUNNELING DEVICES

The physics of the operation of singe-electron tunneling devices (SEDs) and singe-electron tunneling transistors (SETs), especially of those with multiple nanometer-sized islands, has remained poorly understood in spite of some intensive experimental and theoretical research. This computational study examines the current-voltage (IV) characteristics of multi-island single-electron devices using a newly developed multi-island transport simulator (MITS) that is based on semi-classical tunneling theory and kinetic Monte Carlo simulation. The dependence of device characteristics on physical device parameters is explored, and the physical mechanisms that lead to the Coulomb blockade (CB) and Coulomb staircase (CS) characteristics are proposed. Simulations using MITS demonstrate that the overall IV characteristics in a device with a random distribution of islands are a result of a complex interplay among those factors that affect the tunneling rates that are fixed a priori (e.g. island sizes, island separations, temperature, gate bias, etc.), and the evolving charge state of the system, which changes as the source-drain bias (VSD) is changed. With increasing VSD, a multi-island device has to overcome multiple discrete energy barriers (up-steps) before it reaches the threshold voltage (Vth). Beyond Vth, current flow is rate-limited by slow junctions, which leads to the CS structures in the IV characteristic. Each step in the CS is characterized by a unique distribution of island charges with an associated distribution of tunneling probabilities. MITS simulation studies done on one-dimensional (1D) disordered chains show that longer chains are better suited for switching applications as Vth increases with increasing chain length. They are also able to retain CS structures at higher temperatures better than shorter chains. In sufficiently disordered 2D systems, we demonstrate that there may exist a dominant conducting path (DCP) for conduction, which makes the 2D device behave as a quasi-1D device. The existence of a DCP is sensitive to the device structure, but is robust with respect to changes in temperature, gate bias, and VSD. A side gate in 1D and 2D systems can effectively control Vth. We argue that devices with smaller island sizes and narrower junctions may be better suited for practical applications, especially at room temperature.

Bufferless Compression of Asynchronously Sampled ECG Signals in Cubic Hermitian Vector Space.

Asynchronous level crossing sampling analog-to-digital converters (ADCs) are known to be more energy efficient and produce fewer samples than their equidistantly sampling counterparts. However, as the required threshold voltage is lowered, the number of samples and, in turn, the data rate and the energy consumed by the overall system increases. In this paper, we present a cubic Hermitian vector-based technique for online compression of asynchronously sampled electrocardiogram signals. The proposed method is computationally efficient data compression. The algorithm has complexity O(n), thus well suited for asynchronous ADCs. Our algorithm requires no data buffering, maintaining the energy advantage of asynchronous ADCs. The proposed method of compression has a compression ratio of up to 90% with achievable percentage root-mean-square difference ratios as a low as 0.97. The algorithm preserves the superior feature-to-feature timing accuracy of asynchronously sampled signals. These advantages are achieved in a computationally efficient manner since algorithm boundary parameters for the signals are extracted a priori.

Developing the follow-up schedules for women with breast cancer

Background: The follow-up care for women with breast cancer requires an understanding of disease recurrence patterns and the follow-up visit schedule should be determined according to the times when the recurrence are most likely to occur, so that preventive measure can be taken to avoid or minimize the recurrence. Objective: To model breast cancer recurrence through stochastic process with an aim to generate a hazard function for determining a follow-up schedule. Methods: We modeled the process of disease progression as the time transformed Weiner process and the first-hitting-time was used as an approximation of the true failure time. The women's "recurrence-free survival time" or a "not having the recurrence event" is modeled by the time it takes Weiner process to cross a threshold value which represents a woman experiences breast cancer recurrence event. We explored threshold regression model which takes account of covariates that contributed to the prognosis of breast cancer following development of the first-hitting time model. Using real data from SEER-Medicare, we proposed models of follow-up visits schedule on the basis of constant probability of disease recurrence between consecutive visits. Results: We demonstrated that the threshold regression based on first-hitting-time modeling approach can provide useful predictive information about breast cancer recurrence. Our results suggest the surveillance and follow-up schedule can be determined for women based on their prognostic factors such as tumor stage and others. Women with early stage of disease may be seen less frequently for follow-up visits than those women with locally advanced stages. Our results from SEER-Medicare data support the idea of risk-controlled follow-up strategies for groups of women. Conclusion: The methodology we proposed in this study allows one to determine individual follow-up scheduling based on a parametric hazard function that incorporates known prognostic factors.^

Thermal effects in Ni/Au and Mo/Au gate metallization AlGaN/GaN HEMT's reliability

AlGaN/GaN high electron mobility transistors (HEMT) are key devices for the next generation of high-power, high-frequency and high-temperature electronics applications. Although significant progress has been recently achieved [1], stability and reliability are still some of the main issues under investigation, particularly at high temperatures [2-3]. Taking into account that the gate contact metallization is one of the weakest points in AlGaN/GaN HEMTs, the reliability of Ni, Mo, Pt and refractory metal gates is crucial [4-6]. This work has been focused on the thermal stress and reliability assessment of AlGaN/GaN HEMTs. After an unbiased storage at 350 o C for 2000 hours, devices with Ni/Au gates exhibited detrimental IDS-VDS degradation in pulsed mode. In contrast, devices with Mo/Au gates showed no degradation after similar storage conditions. Further capacitance-voltage characterization as a function of temperature and frequency revealed two distinct trap-related effects in both kinds of devices. At low frequency (< 1MHz), increased capacitance near the threshold voltage was present at high temperatures and more pronounced for the Ni/Au gate HEMT and as the frequency is lower. Such an anomalous “bump” has been previously related to H-related surface polar charges [7]. This anomalous behavior in the C-V characteristics was also observed in Mo/Au gate HEMTs after 1000 h at a calculated channel temperatures of around from 250 o C (T2) up to 320 ºC (T4), under a DC bias (VDS= 25 V, IDS= 420 mA/mm) (DC-life test). The devices showed a higher “bump” as the channel temperature is higher (Fig. 1). At 1 MHz, the higher C-V curve slope of the Ni/Au gated HEMTs indicated higher trap density than Mo/Au metallization (Fig. 2). These results highlight that temperature is an acceleration factor in the device degradation, in good agreement with [3]. Interface state density analysis is being performed in order to estimate the trap density and activation energy.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Four-injector variability modeling of FinFET predictive technology models

The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. In this work we apply the four-injector approach for variability modeling to the simulation of SRAMs with predictive technology models from 20nm down to 7nm nodes. We show that the SRAMs, designed following ITRS roadmap, present stability metrics higher by at least 20% compared to a classical variability modeling approach. Speed estimation is also pessimistic, whereas leakage is underestimated if sub-threshold slope and DIBL mismatch and their correlations with threshold voltage are not considered.

A trace component of ginseng that inhibits Ca2+ channels through a pertussis toxin-sensitive G protein.

A crude extract from ginseng root inhibits high-threshold, voltage-dependent Ca2+ channels through an unknown receptor linked to a pertussis toxin-sensitive G protein. We now have found the particular compound that seems responsible for the effect: it is a saponin, called ginsenoside Rf (Rf), that is present in only trace amounts within ginseng. At saturating concentrations, Rf rapidly and reversibly inhibits N-type, and other high-threshold, Ca2+ channels in rat sensory neurons to the same degree as a maximal dose of opioids. The effect is dose-dependent (half-maximal inhibition: 40 microM) and it is virtually eliminated by pretreatment of the neurons with pertussis toxin, an inhibitor of G(o) and Gi GTP-binding proteins. Other ginseng saponins--ginsenosides Rb1, Rc, Re, and Rg1--caused relatively little inhibition of Ca2+ channels, and lipophilic components of ginseng root had no effect. Antagonists of a variety of neurotransmitter receptors that inhibit Ca2+ channels fail to alter the effect of Rf, raising the possibility that Rf acts through another G protein-linked receptor. Rf also inhibits Ca2+ channels in the hybrid F-11 cell line, which might, therefore, be useful for molecular characterization of the putative receptor for Rf. Because it is not a peptide and it shares important cellular and molecular targets with opioids, Rf might be useful in itself or as a template for designing additional modulators of neuronal Ca2+ channels.

When does leverage hurt productivity growth? A firm-level analysis:a firm-level analysis

In the wake of the global financial crisis, several macroeconomic contributions have highlighted the risks of excessive credit expansion. In particular, too much finance can have a negative impact on growth. We examine the microeconomic foundations of this argument, positing a non-monotonic relationship between leverage and firm-level productivity growth in the spirit of the trade-off theory of capital structure. A threshold regression model estimated on a sample of Central and Eastern European countries confirms that TFP growth increases with leverage until the latter reaches a critical threshold beyond which leverage lowers TFP growth. This estimate can provide guidance to firms and policy makers on identifying "excessive" leverage. We find similar non-monotonic relationships between leverage and proxies for firm value. Our results are a first step in bridging the gap between the literature on optimal capital structure and the wider macro literature on the finance-growth nexus. © 2012 Elsevier Ltd.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Trapping phenomena in AlGaN and InAlN barrier HEMTs with different geometries

PAPER Trapping phenomena in AlGaN and InAlN barrier HEMTs with different geometries S Martin-Horcajo1, A Wang1, A Bosca1, M F Romero1, M J Tadjer1,2, A D Koehler2, T J Anderson2 and F Calle1 Published 11 February 2015 • © 2015 IOP Publishing Ltd Semiconductor Science and Technology, Volume 30, Number 3 Article PDF Figures References Citations Metrics 350 Total downloads Cited by 1 articles Export citation and abstract BibTeX RIS Turn on MathJax Share this article Article information Abstract Trapping effects were evaluated by means of pulsed measurements under different quiescent biases for GaN/AlGaN/GaN and GaN/InAlN/GaN. It was found that devices with an AlGaN barrier underwent an increase in the on-resistance, and a drain current and transconductance reduction without measurable threshold voltage change, suggesting the location of the traps in the gate-drain access region. In contrast, devices with an InAlN barrier showed a transconductance and a decrease in drain associated with a significant positive shift of threshold voltage, indicating that the traps were likely located under the gate region; as well as an on-resistance degradation probably associated with the presence of surface traps in the gate-drain access region. Furthermore, measurements of drain current transients at different ambient temperatures revealed that the activation energy of electron traps was 0.43 eV and 0.38 eV for AlGaN and InAlN barrier devices, respectively. Experimental and simulation results demonstrated the influence of device geometry on the observed trapping effects, since devices with larger gate lengths and gate-to-drain distance values exhibited less noticeable charge trapping effects.

Improved Electronics for the Hall A Detectors at JLab: Summing Modules and VDC Amplifier/Discriminator Cards

Testing of summing electronics and VDC A/D Cards was performed to assure proper functioning and operation within defined parameters. In both the summing modules and the VDC A/D cards, testing for minimum threshold voltage for each channel and crosstalk between neighboring channels was performed. Additionally, the modules were installed in Hall A with input signals from shower detectors arranged to establish a trigger by summing signals together with the use of tested modules. Testing involved utilizing a pulser to mimic PMT signals, a discriminator, an attenuator, a scaler, a level translator, an oscilloscope, a high voltage power supply, and a special apparatus used to power and send signal to the A/D cards. After testing, modules were obtained that meet necessary criteria for use in the APEX experiment, and the A/D cards obtained were determined to have adequate specifications for their utilization, with specific results included in the appendix.

Rufinamide Attenuates Mechanical Allodynia in a Model of Neuropathic Pain in the Mouse and Stabilizes Voltage-gated Sodium Channel Inactivated State.

BACKGROUND:: Voltage-gated sodium channels dysregulation is important for hyperexcitability leading to pain persistence. Sodium channel blockers currently used to treat neuropathic pain are poorly tolerated. Getting new molecules to clinical use is laborious. We here propose a drug already marketed as anticonvulsant, rufinamide. METHODS:: We compared the behavioral effect of rufinamide to amitriptyline using the Spared Nerve Injury neuropathic pain model in mice. We compared the effect of rufinamide on sodium currents using in vitro patch clamp in cells expressing the voltage-gated sodium channel Nav1.7 isoform and on dissociated dorsal root ganglion neurons to amitriptyline and mexiletine. RESULTS:: In naive mice, amitriptyline (20 mg/kg) increased withdrawal threshold to mechanical stimulation from 1.3 (0.6-1.9) (median [95% CI]) to 2.3 g (2.2-2.5) and latency of withdrawal to heat stimulation from 13.1 (10.4-15.5) to 30.0 s (21.8-31.9), whereas rufinamide had no effect. Rufinamide and amitriptyline alleviated injury-induced mechanical allodynia for 4 h (maximal effect: 0.10 ± 0.03 g (mean ± SD) to 1.99 ± 0.26 g for rufinamide and 0.25 ± 0.22 g to 1.92 ± 0.85 g for amitriptyline). All drugs reduced peak current and stabilized the inactivated state of voltage-gated sodium channel Nav1.7, with similar effects in dorsal root ganglion neurons. CONCLUSIONS:: At doses alleviating neuropathic pain, amitriptyline showed alteration of behavioral response possibly related to either alteration of basal pain sensitivity or sedative effect or both. Side-effects and drug tolerance/compliance are major problems with drugs such as amitriptyline. Rufinamide seems to have a better tolerability profile and could be a new alternative to explore for the treatment of neuropathic pain.

Rufinamide attenuates mechanical allodynia in a model of neuropathic pain in the mouse and stabilizes voltage-gated sodium channel inactivated state

Background: Voltage-gated sodium channels dysregulation is important for hyperexcitability leading to pain persistence. Sodium channel blockers currently used to treat neuropathic pain are poorly tolerated. Getting new molecules to clinical use is laborious. We here propose a drug already marketed as anticonvulsant, rufinamide. Methods: We compared the behavioral effect of rufinamide to amitriptyline using the Spared Nerve Injury neuropathic pain model in mice. We compared the effect of rufinamide on sodium currents using in vitro patch clamp in cells expressing the voltage-gated sodium channel Nav1.7 isoform and on dissociated dorsal root ganglion neurons to amitriptyline and mexiletine. Results: In naive mice, amitriptyline (20 mg/kg) increased withdrawal threshold to mechanical stimulation from 1.3 (0.6–1.9) (median [95% CI]) to 2.3 g (2.2–2.5) and latency of withdrawal to heat stimulation from 13.1 (10.4–15.5) to 30.0 s (21.8–31.9), whereas rufinamide had no effect. Rufinamide and amitriptyline alleviated injury-induced mechanical allodynia for 4 h (maximal effect: 0.10 ± 0.03 g (mean ± SD) to 1.99 ± 0.26 g for rufinamide and 0.25 ± 0.22 g to 1.92 ± 0.85 g for amitriptyline). All drugs reduced peak current and stabilized the inactivated state of voltage-gated sodium channel Nav1.7, with similar effects in dorsal root ganglion neurons. Conclusions: At doses alleviating neuropathic pain, amitriptyline showed alteration of behavioral response possibly related to either alteration of basal pain sensitivity or sedative effect or both. Side-effects and drug tolerance/compliance are major problems with drugs such as amitriptyline. Rufinamide seems to have a better tolerability profile and could be a new alternative to explore for the treatment of neuropathic pain.

Brownian motion with drift threshold model

In this thesis we implement estimating procedures in order to estimate threshold parameters for the continuous time threshold models driven by stochastic di®erential equations. The ¯rst procedure is based on the EM (expectation-maximization) algorithm applied to the threshold model built from the Brownian motion with drift process. The second procedure mimics one of the fundamental ideas in the estimation of the thresholds in time series context, that is, conditional least squares estimation. We implement this procedure not only for the threshold model built from the Brownian motion with drift process but also for more generic models as the ones built from the geometric Brownian motion or the Ornstein-Uhlenbeck process. Both procedures are implemented for simu- lated data and the least squares estimation procedure is also implemented for real data of daily prices from a set of international funds. The ¯rst fund is the PF-European Sus- tainable Equities-R fund from the Pictet Funds company and the second is the Parvest Europe Dynamic Growth fund from the BNP Paribas company. The data for both funds are daily prices from the year 2004. The last fund to be considered is the Converging Europe Bond fund from the Schroder company and the data are daily prices from the year 2005.