849 resultados para power Consumption


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Power capping is a fundamental method for reducing the energy consumption of a wide range of modern computing environments, ranging from mobile embedded systems to datacentres. Unfortunately, maximising performance and system efficiency under static power caps remains challenging, while maximising performance under dynamic power caps has been largely unexplored. We present an adaptive power capping method that reduces the power consumption and maximizes the performance of heterogeneous SoCs for mobile and server platforms. Our technique combines power capping with coordinated DVFS, data partitioning and core allocations on a heterogeneous SoC with ARM processors and FPGA resources. We design our framework as a run-time system based on OpenMP and OpenCL to utilise the heterogeneous resources. We evaluate it through five data-parallel benchmarks on the Xilinx SoC which allows fully voltage and frequency control. Our experiments show a significant performance boost of 30% under dynamic power caps with concurrent execution on ARM and FPGA, compared to a naive separate approach.

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This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

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Thesis (Ph.D.)--University of Washington, 2016-03

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The use of Electric Vehicles (EVs) will change significantly the planning and management of power systems in a near future. This paper proposes a real-time tariff strategy for the charge process of the EVs. The main objective is to evaluate the influence of real-time tariffs in the EVs owners’ behaviour and also the impact in load diagram. The paper proposes the energy price variation according to the relation between wind generation and power consumption. The proposed strategy was tested in two different days in the Danish power system. January 31st and August 13th 2013 were selected because of the high quantities of wind generation. The main goal is to evaluate the changes in the EVs charging diagram with the energy price preventing wind curtailment.

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La présence importante de plusieurs réseaux sans-fils de différentes portées a encouragée le développement d’une nouvelle génération d’équipements portables sans-fils avec plusieurs interfaces radio. Ainsi, les utilisateurs peuvent bénéficier d’une large possibilité de connectivité aux réseaux sans-fils (e.g. Wi-Fi [1], WiMAX [2], 3G [3]) disponibles autour. Cependant, la batterie d’un nœud mobile à plusieurs interfaces sera rapidement épuisée et le temps d’utilisation de l’équipement sera réduit aussi. Pour prolonger l’utilisation du mobile les standards, des réseaux sans-fils, on définie (individuellement) plusieurs états (émission, réception, sleep, idle, etc.); quand une interface radio n’est pas en mode émission/réception il est en mode sleep/idle où la consommation est très faible, comparée aux modes émission/réception. Pourtant, en cas d’équipement portable à multi-interfaces radio, l’énergie totale consommée par les interfaces en mode idle est très importante. Autrement, un équipement portable équipé de plusieurs interfaces radio augmente sa capacité de connectivité mais réduit sa longévité d’utilisation. Pour surpasser cet inconvénient on propose une plate-forme, qu'on appelle IMIP (Integrated Management of Interface Power), basée sur l’extension du standard MIH (Media Independent Handover) IEEE 802.21 [4]. IMIP permet une meilleure gestion d’énergie des interfaces radio, d’un équipement mobile à multi-radio, lorsque celles-ci entrent en mode idle. Les expérimentations que nous avons exécutées montrent que l’utilisation de IMIP permet d'économiser jusqu'a 80% de l'énergie consommée en comparaison avec les standards existants. En effet, IMIP permet de prolonger la durée d'utilisation d'équipements à plusieurs interfaces grâce à sa gestion efficace de l'énergie.

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This paper deals with the energy consumption and the evaluation of the performance of air supply systems for a ventilated room involving high- and low-level supplies. The energy performance assessment is based on the airflow rate, which is related to the fan power consumption by achieving the same environmental quality performance for each case. Four different ventilation systems are considered: wall displacement ventilation, confluent jets ventilation, impinging jet ventilation and a high level mixing ventilation system. The ventilation performance of these systems will be examined by means of achieving the same Air Distribution Index (ADI) for different cases. The widely used high-level supplies require much more fan power than those for low-level supplies for achieving the same value of ADI. In addition, the supply velocity, hence the supply dynamic pressure, for a high-level supply is much larger than for low-level supplies. This further increases the power consumption for high-level supply systems. The paper considers these factors and attempts to provide some guidelines on the difference in the energy consumption associated with high and low level air supply systems. This will be useful information for designers and to the authors' knowledge there is a lack of information available in the literature on this area of room air distribution. The energy performance of the above-mentioned ventilation systems has been evaluated on the basis of the fan power consumed which is related to the airflow rate required to provide equivalent indoor environment. The Air Distribution Index (ADI) is used to evaluate the indoor environment produced in the room by the ventilation strategy being used. The results reveal that mixing ventilation requires the highest fan power and the confluent jets ventilation needs the lowest fan power in order to achieve nearly the same value of ADI.

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Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

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This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

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This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

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Cloud computing is usually regarded as being energy efficient and thus emitting less greenhouse gases (GHG) than traditional forms of computing. When the energy consumption of Microsoft’s cloud computing Office 365 (O365) and traditional Office 2010 (O2010) software suites were tested and modeled, some cloud services were found to consume more energy than the traditional form. The developed model in this research took into consideration the energy consumption at the three main stages of data transmission; data center, network, and end user device. Comparable products from each suite were selected and activities were defined for each product to represent a different computing type. Microsoft provided highly confidential data for the data center stage, while the networking and user device stages were measured directly. A new measurement and software apportionment approach was defined and utilized allowing the power consumption of cloud services to be directly measured for the user device stage. Results indicated that cloud computing is more energy efficient for Excel and Outlook which consumed less energy and emitted less GHG than the standalone counterpart. The power consumption of the cloud based Outlook (8%) and Excel (17%) was lower than their traditional counterparts. However, the power consumption of the cloud version of Word was 17% higher than its traditional equivalent. A third mixed access method was also measured for Word which emitted 5% more GHG than the traditional version. It is evident that cloud computing may not provide a unified way forward to reduce energy consumption and GHG. Direct conversion from the standalone package into the cloud provision platform can now consider energy and GHG emissions at the software development and cloud service design stage using the methods described in this research.

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The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

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This work uses a monitoring system based on a PC platform, where the acoustic emission and electric power signals generated during the grinding process are used to investigate superficial burning occurrence in a surface grinding operation using two types of steel, three grinding conditions and an Al203 vitrified grinding wheel. Acoustic emission signals on the workpiece and grinding power were measured during a surface plunge operation until the grinding burn happened. From the results the standard deviation of the acoustic emission signal and the maximum electric power were calculated for each grinding pass. The proposed DPO parameter is the product between the power level and acoustic emission standard deviation. The results show that both signals can be used for burning detection, and the parameter DPO is the best indicator for the burning studied in this work. This can be explained by the high dispersion of the acoustic emission RMS level associated to the high power consumption when the grinding wheel lose its sharpness.

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In June 2001, after a dry period, the level of the water reservoirs in Brazil was below their operational levels. This situation, combined with other historical factors, led the country into a period of power rationing. As expected, power consumption lowered during this period. After December 2001, when the power rationing ended, electrical utilities expected to return to their normal power consumption in a matter of months, but the level of power consumption only returned to its level around years 2004 2005. Consumer behavior went through a change during this period, and the consumers kept this behavior after, leading to electrical and economical consequences until today. This paper presents an analysis of several factors that led to these events, including historical consumption data and comparisons with similar situations. The objective of this analysis is to give helpful information to electrical utilities, that could deal with similar situations, in their load forecasting studies. © 2006 IEEE.

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Considering the Conservative Power Theory (CPT), this paper proposes some novel compensation strategies for shunt passive or active devices. The CPT current decompositions result in several current terms, which are associated with specific physical phenomena (average power consumption P, energy storage Q, load and source distortion D, unbalances N). These current components were used in this work for the definition of different current compensators, which can be selective in terms of minimizing particular disturbing effects. Compensation strategies for single and three-phase four-wire circuits have also been considered. Simulation results have been demonstrated in order to validate the possibilities and performance of the proposed strategies. © 2010 IEEE.

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Based on the framework of the Conservative Power Theory (CPT), this paper proposes some compensation strategies for shunt current compensators. CPT current decompositions result in several current-related terms associated with specific load characteristics, such as power consumption, energy storage, unbalances and load nonlinearities. These current components are decoupled (orthogonal) from each other and are used here to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Compensation strategies for single- and three-phase four-wire circuits are also considered. Simulated and experimental results are described to validate the possibilities and performance of the proposed strategies. © 2013 Brazilian Society for Automatics - SBA.