953 resultados para poset of Hausdorff topologies
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Let (X, d) be a metric space and CL(X) the family of all nonempty closed subsets of X. We provide a new proof of the fact that the coincidence of the Vietoris and Wijsman topologies induced by the metric d forces X to be a compact space. In the literature only a more involved and indirect proof using the proximal topology is known. Here we do not need this intermediate step. Moreover we prove that (X, d) is boundedly compact if and only if the bounded Vietoris and Wijsman topologies on CL(X) coincide.
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Mathematics Subject Classification: 44A05, 46F12, 28A78
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ACM Computing Classification System (1998): G.1.2.
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2000 Mathematics Subject Classification: 46B50, 46B70, 46G12.
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El presente trabajo consiste en dos partes diferenciadas: la principal de ellas (Cap tulos 1 y 2) est a dedicada a introducir estructura adicional en grupos que aparecen de manera natural en el contexto de la teor a de la forma. En la segunda parte (Cap tulo 3), se plantea c omo generalizar la teor a de espacios recubridores y, en particular, se propone una l nea de trabajo relacionada con la teor a de la forma. El punto de partida de esta tesis doctoral son los trabajos [25, 26, 68, 69, 70] en los que los autores introducen y utilizan algunas ultram etricas en el conjunto de los mor smos shape entre dos espacios topol ogicos punteados. En particular, si el dominio es (S1; 1); la construcci on realizada en [68] permite explicitar una ultram etrica en el grupo shape 1(X; x0) de un espacio m etrico compacto X; como ya fue observado en [69] y [80]. Si el espacio no es m etrico compacto, la construcci on nos lleva a utilizar el concepto de ultram etrica generalizada, en el sentido de Priess-Crampe y Ribenboim [78, 79]. En [7], D. K. Biss introduce la idea de topologizar el grupo fundamental de un espacio, de forma que la topolog a en 1(X; x0) sea una topolog a de grupo que permita detectar la (no) existencia de un recubridor universal para X: La forma de proceder sugerida es tomar en 1(X; x0)la toplog a cociente inducida por la topolog a compacto-abierta en el espacio de lazos (X; x0): Sin embargo, hay algunos errores en el art culo mencionado: en concreto, el error relacionado con el presente trabajo fue puesto de mani esto por P. Fabel en [33], mostrando que, en general, la operaci on de grupo en 1(X; x0)con la topolog a cociente no es continua. Utilizando un punto de vista similar, varios autores han tratado de dotar al grupo fundamental con una topolog a, de forma que 1(X; x0) sea un grupo topol ogico y la proyecci on q (X; x0){u100000} 1(X; x0)sea continua...
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This paper continues the study of spectral synthesis and the topologies τ∞ and τr on the ideal space of a Banach algebra, concentrating on the class of Banach *-algebras, and in particular on L1-group algebras. It is shown that if a group G is a finite extension of an abelian group then τr is Hausdorff on the ideal space of L1(G) if and only if L1(G) has spectral synthesis, which in turn is equivalent to G being compact. The result is applied to nilpotent groups, [FD]−-groups, and Moore groups. An example is given of a non-compact, non-abelian group G for which L1(G) has spectral synthesis. It is also shown that if G is a non-discrete group then τr is not Hausdorff on the ideal lattice of the Fourier algebra A(G).
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For a topological vector space (X, τ ), we consider the family LCT (X, τ ) of all locally convex topologies defined on X, which give rise to the same continuous linear functionals as the original topology τ . We prove that for an infinite-dimensional reflexive Banach space (X, τ ), the cardinality of LCT (X, τ ) is at least c.
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Voltage imbalance in capacitors is a well-known problem in compensator topologies which use two or more capacitors. This imbalance may exist even if the load does not contain any DC component, due to practical factors. However, when the load contains a DC part, the voltage imbalance problem becomes critical. In this paper, a two-quadrant chopper has been used to regulate the capacitor voltages in a two-capacitor compensator structure. Two different control strategies for the two-quadrant chopper to equalize the voltage of the capacitors have been proposed. The strategies are validated through detailed simulation studies. Experiments have also been carried out to validate the hysteresis control of chopper.
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AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.
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The DNA of three biological variants, G1, Ic and G2, which originated from the same greenhouse isolate of rice tungro bacilliform virus (RTBV) at the International Rice Research Institute (IRRI), was cloned and sequenced. Comparison of the sequences revealed small differences in genome sizes. The variants were between 95 and 99% identical at the nucleotide and amino acid levels. Alignment of the three genome sequences with those of three published RTBV sequences (Phi-1, Phi-2 and Phi-3) revealed numerous nucleotide substitutions and some insertions and deletions. The published RTBV sequences originated from the same greenhouse isolate at IRRI 20, 11 and 9 years ago. All open reading frames (ORFs) and known functional domains were conserved across the six variants. The cysteine-rich region of ORF3 showed the greatest variation. When the six DNA sequences from IRRI were compared with that of an isolate from Malaysia (Serdang), similar changes were observed in the cysteine-rich region in addition to other nucleotide substitutions and deletions across the genome. The aligned nucleotide sequences of the IRRI variants and Serdang were used to analyse phylogenetic relationships by the bootstrapped parsimony, distance and maximum-likelihood methods. The isolates clustered in three groups: Serdang alone; Ic and G1; and Phi-1, Phi-2, Phi-3 and G2. The distribution of phylogenetically informative residues in the IRRI sequences shared with the Serdang sequence and the differing tree topologies for segments of the genome suggested that recombination, as well as substitutions and insertions or deletions, has played a role in the evolution of RTBV variants. The significance and implications of these evolutionary forces are discussed in comparison with badnaviruses and caulimoviruses.
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Distributed Genetic Algorithms (DGAs) designed for the Internet have to take its high communication cost into consideration. For island model GAs, the migration topology has a major impact on DGA performance. This paper describes and evaluates an adaptive migration topology optimizer that keeps the communication load low while maintaining high solution quality. Experiments on benchmark problems show that the optimized topology outperforms static or random topologies of the same degree of connectivity. The applicability of the method on real-world problems is demonstrated on a hard optimization problem in VLSI design.
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Advanced substation applications, such as synchrophasors and IEC 61850-9-2 sampled value process buses, depend upon highly accurate synchronizing signals for correct operation. The IEEE 1588 Precision Timing Protocol (PTP) is the recommended means of providing precise timing for future substations. This paper presents a quantitative assessment of PTP reliability using Fault Tree Analysis. Two network topologies are proposed that use grandmaster clocks with dual network connections and take advantage of the Best Master Clock Algorithm (BMCA) from IEEE 1588. The cross-connected grandmaster topology doubles reliability, and the addition of a shared third grandmaster gives a nine-fold improvement over duplicated grandmasters. The performance of BMCA mediated handover of the grandmaster role during contingencies in the timing system was evaluated experimentally. The 1 µs performance requirement of sampled values and synchrophasors are met, even during network or GPS antenna outages. Slave clocks are shown to synchronize to the backup grandmaster in response to degraded performance or loss of the main grandmaster. Slave disturbances are less than 350 ns provided the grandmaster reference clocks are not offset from one another. A clear understanding of PTP reliability and the factors that affect availability will encourage the adoption of PTP for substation time synchronization.
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Computer worms represent a serious threat for modern communication infrastructures. These epidemics can cause great damage such as financial losses or interruption of critical services which support lives of citizens. These worms can spread with a speed which prevents instant human intervention. Therefore automatic detection and mitigation techniques need to be developed. However, if these techniques are not designed and intensively tested in realistic environments, they may cause even more harm as they heavily interfere with high volume communication flows. We present a simulation model which allows studies of worm spread and counter measures in large scale multi-AS topologies with millions of IP addresses.
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New residential scale photovoltaic (PV) arrays are commonly connected to the grid by a single dc-ac inverter connected to a series string of pv panels, or many small dc-ac inverters which connect one or two panels directly to the ac grid. This paper proposes an alternative topology of nonisolated per-panel dc-dc converters connected in series to create a high voltage string connected to a simplified dc-ac inverter. This offers the advantages of a "converter-per-panel" approach without the cost or efficiency penalties of individual dc-ac grid connected inverters. Buck, boost, buck-boost, and Cu´k converters are considered as possible dc-dc converters that can be cascaded. Matlab simulations are used to compare the efficiency of each topology as well as evaluating the benefits of increasing cost and complexity. The buck and then boost converters are shown to be the most efficient topologies for a given cost, with the buck best suited for long strings and the boost for short strings. While flexible in voltage ranges, buck-boost, and Cu´k converters are always at an efficiency or alternatively cost disadvantage.
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Grid connected photovoltaic (PV) inverters fall into three broad categories - central, string and module integrated converters (MICs). MICs offer many advantages in performance and flexibility, but are at a cost disadvantage. Two alternative novel approaches proposed by the author - cascaded dc-dc MICs and bypass dc-dc MICs - integrate a simple non-isolated intelligent dc-dc converter with each PV module to provide the advantages of dc-ac MICs at a lower cost. A suitable universal 150 W 5 A dc-dc converter design is presented based on two interleaved MOSFET half bridges. Testing shows zero voltage switching (ZVS) keeps losses under 1 W for bi-directional power flows up to 15 W between two adjacent 12 V PV modules for the bypass application, and efficiencies over 94% for most of the operational power range for the cascaded converter application. Based on the experimental results, potential optimizations to further reduce losses are discussed.