A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Large-scale, uniform DNA network on 11-mercaptoundecanoic acid modified gold (111) surface: Atomic force microscopy study

Large-scale, uniform plasmid deoxyribonucleic acid (DNA) network has been successfully constructed on 11-mercaptoundecanoic acid modified gold (111) surface using a self-assembly technique. The effect of DNA concentration on the characteristics of the DNA network was investigated by atomic force microscopy. It was found that the size of meshes and the height of fibers in the DNA network could be controlled by varying the concentration of DNA with a constant time of assembly of 24 h.

On-chip electron-impact ion source using carbon nanotube field emitters

A lateral on-chip electron-impact ion source utilizing a carbon nanotube field emission electron source was fabricated and characterized. The device consists of a cathode with aligned carbon nanotubes, a control grid, and an ion collector electrode. The electron-impact ionization of He, Ar, and Xe was studied as a function of field emission current and pressure. The ion current was linear with respect to gas pressure from 10-4 to 10-1 Torr. The device can operate as a vacuum ion gauge with a sensitivity of approximately 1 Torr-1. Ion currents in excess of 1 μA were generated. © 2007 American Institute of Physics.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

GELIFICATION - A SIMPLE AND EFFICIENT METHOD FOR ON-CHIP STORAGE OF REAGENTS: TOWARDS LAB-ON-A-CHIP SYSTEMS FOR POINT-OF-CARE DIAGNOSTICS

In this study, we describe a simple and efficient method for on-chip storage of reagents for point-of-care (POC) diagnostics. The method is based on gelification of all reagents required for on-chip PCR-based diagnostics as a ready-to-use product. The result reported here is a key step towards the development of a ready and easy to use fully integrated Lab-on-a-chip (LOC) system for fast, cost-effective and efficient POC diagnostics analysis.