Self-healing Techniques for RF and mm-Wave Transmitters and Receivers

With continuing advances in CMOS technology, feature sizes of modern Silicon chip-sets have gone down drastically over the past decade. In addition to desktops and laptop processors, a vast majority of these chips are also being deployed in mobile communication devices like smart-phones and tablets, where multiple radio-frequency integrated circuits (RFICs) must be integrated into one device to cater to a wide variety of applications such as Wi-Fi, Bluetooth, NFC, wireless charging, etc. While a small feature size enables higher integration levels leading to billions of transistors co-existing on a single chip, it also makes these Silicon ICs more susceptible to variations. A part of these variations can be attributed to the manufacturing process itself, particularly due to the stringent dimensional tolerances associated with the lithographic steps in modern processes. Additionally, RF or millimeter-wave communication chip-sets are subject to another type of variation caused by dynamic changes in the operating environment. Another bottleneck in the development of high performance RF/mm-wave Silicon ICs is the lack of accurate analog/high-frequency models in nanometer CMOS processes. This can be primarily attributed to the fact that most cutting edge processes are geared towards digital system implementation and as such there is little model-to-hardware correlation at RF frequencies.

All these issues have significantly degraded yield of high performance mm-wave and RF CMOS systems which often require multiple trial-and-error based Silicon validations, thereby incurring additional production costs. This dissertation proposes a low overhead technique which attempts to counter the detrimental effects of these variations, thereby improving both performance and yield of chips post fabrication in a systematic way. The key idea behind this approach is to dynamically sense the performance of the system, identify when a problem has occurred, and then actuate it back to its desired performance level through an intelligent on-chip optimization algorithm. We term this technique as self-healing drawing inspiration from nature's own way of healing the body against adverse environmental effects. To effectively demonstrate the efficacy of self-healing in CMOS systems, several representative examples are designed, fabricated, and measured against a variety of operating conditions.

We demonstrate a high-power mm-wave segmented power mixer array based transmitter architecture that is capable of generating high-speed and non-constant envelope modulations at higher efficiencies compared to existing conventional designs. We then incorporate several sensors and actuators into the design and demonstrate closed-loop healing against a wide variety of non-ideal operating conditions. We also demonstrate fully-integrated self-healing in the context of another mm-wave power amplifier, where measurements were performed across several chips, showing significant improvements in performance as well as reduced variability in the presence of process variations and load impedance mismatch, as well as catastrophic transistor failure. Finally, on the receiver side, a closed-loop self-healing phase synthesis scheme is demonstrated in conjunction with a wide-band voltage controlled oscillator to generate phase shifter local oscillator (LO) signals for a phased array receiver. The system is shown to heal against non-idealities in the LO signal generation and distribution, significantly reducing phase errors across a wide range of frequencies.

A four-passed ytterbium-doped fiber amplifier

In this paper, a four-passed ytterbium-doped fiber amplifier (YDFA) is discussed. The gain and the pump and the signal light propagation characteristics of the four-passed YDFA are described. It is found that, while using a shorter length of the fiber, a four-passed fiber amplifier can realize the same output power as a single-pass fiber amplifier, and, for the same fiber lengths, a four-passed fiber amplifier offers a significantly higher power than its single-pass counterpart. (C) 2006 Elsevier Ltd. All rights reserved.

APSK coded modulation schemes for nonlinear satellite channels with high power and spectral efficiency

A new class of 16-ary Amplitude Phase Shift Keying (APSK) coded modulations deemed double-ring PSK modulations best suited for (satellite) nonlinear channels is proposed. Constellation parameters optimization has been based on geometric and information-theoretic considerations. Furthermore, pre- and post-compensation techniques to reduce the nonlinearity impact have been examined. Digital timing clock and carrier phase have been derived and analyzed for a Turbo coded version of the same new modulation scheme. Finally, the performance of state-of the art Turbo coded modulation for this new 16-ary digital modulation has been investigated and compared to the known TCM schemes. It is shown that for the same coding scheme, double-ring APSK modulation outperforms classical 16-QAM and 16-PSK over a typical satellite nonlinear channel due to its intrinsic robustness against the High Power Amplifier (HPA) nonlinear characteristics. The new modulation is shown to be power- and spectrally-efficient, with interesting applications to satellite communications. © 2002 by the American Institute of Aeronautics and Astronautics, Inc.

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

Analysis and Design of Class-E3F and Transmission-Line Class-E3F2 Power Amplifiers

In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F2 and transmission-line (TL) Class-E3 F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3 F PA are described. The load networks of the Class-E3 F and TL Class-E 3 F2amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. © 2010 IEEE.

Integrated Low-Loss Passive SiGe Power Splitter and Combiner Operating Across 78-86 GHz Band

This paper describes the design, implementation, and characterization of a new type of passive power splitting and combining structure for use in a differential four-way power-combining amplifier operating at E-band. In order to achieve lowest insertion loss, input and output coils inductances are resonated with shunt capacitances. Simple C-L-C and L-C networks are proposed in order to compensate inductive loading due to routing line that would otherwise introduce mismatch and increase loss. Across 78-86 GHz band, measured insertion loss is about 7 dB. Measured return losses are >10 dB from 73 GHz to 94 GHz at the input port and >9 dB from 60 GHz to 94 GHz at the output port. When integrated with driver and power amplifier cells, the simulated complete circuit exhibits 18.2 dB gain and 20.3 dBm saturated output power.

Holistic design of 8-way combining transformers in SiGe technology for use in millimetre-wave power amplifiers

This paper presents the design of a novel 8-way power-combining transformer for use in mm-wave power amplifier (PA). The combiner exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. A complete circuit comprised of a power splitter, two-stage cascode PA array, a power combiner and input/output matching elements was designed and realized in SiGe technology. Measured gain of at least 16.8 dB was obtained from 76.4 GHz to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm OP and 14 dBm saturated output power when operated from a 3.2 V DC supply voltage at 78 GHz. © 2013 IEEE.

High-Efficiency Harmonic-Peaking Class-EF Power Amplifiers with Enhanced Maximum Operating Frequency

The recently introduced Class-EF power amplifier (PA) has a peak switch voltage lower than that of the Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. Consequently, soft-switching operation that minimizes power dissipation during off-to-on transition cannot be achieved at high frequencies. Two new Class-EF PA variants with transmission-line load networks, namely, third-harmonic-peaking (THP) and fifth-harmonic-peaking (FHP) Class-EF PAs are proposed in this paper. These permit operation at higher frequencies at no expense to other PA figures of merit. Analytical expressions are derived in order to obtain circuit component values, which satisfy the required Class-EF impedances at fundamental frequency, all even harmonics, and the first few odd harmonics as well as simultaneously providing impedance matching to a 50- Ω load. Furthermore, a novel open-circuit and shorted stub arrangement, which has substantial practical benefits, is proposed to replace the normal quarter-wave line connected at the transistor's drain. Using GaN HEMTs, two PA prototypes were built. Measured peak drain efficiency of 91% and output power of 39.5 dBm were obtained at 2.22 GHz for the THP Class-EF PA. The FHP Class-EF PA delivered output power of 41.9 dBm with 85% drain efficiency at 1.52 GHz.

Peak to average power ratio analysis for LTE systems

The 3rd generation partnership project (3GPP) long term evolution (LTE) standard uses single carrier frequency division multiple access (SCFDMA) scheme for the uplink transmissions and orthogonal frequency division multiplexing access (OFDMA) in downlink. SCFDMA uses DFT spreading prior to OFDMA modulation to map the signal from each user to a subset of the available subcarriers i.e., single carrier modulation. The efficiency of a power amplifier is determined by the peak to average power ratio (PAPR) of the modulated signal. In this paper, we analyze the PAPR in 3GPP LTE systems using root raised cosine based filter. Simulation results show that the SCFDMA subcarrier mapping has a significantly lower PAPR compared to OFDMA. Also comparing the three forms of SCFDMA subcarrier mapping, results show that interleave FDMA (IFDMA) subcarrier mapping with proposed root raised cosine filter reduced PAPR significantly than localized FDMA (LFDMA) and distributed (DFDMA) mapping. This improves its radio frequency (RF) power amplifier efficiency and also the mean power output from a battery driven mobile terminal.

Series combination of a switched dc-dc converter and a linear regulator for high frequency RF envelope amplifier

Classical linear amplifiers such as A, AB and B offer very good linearity suitable for RF power amplifiers. However, its inherent low efficiency limits its use especially in base-stations that manage tens or hundreds of Watts. The use of linearization techniques such as Envelope Elimination and Restoration (EER) allow an increase of efficiency keeping good linearity. This technique requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier. In this paper, several alternatives are analyzed to implement the envelope amplifier based on a cascade association of a switched dc-dc converter and a linear regulator. A simplified version of this approach is also suitable to operate with Envelope Tracking technique.

Envelope amplifier based on switching capacitors for high efficiency RF amplifiers

Modern transmitters usually have to amplify and transmit signals with simultaneous envelope and phase modulation. Due to this property of the transmitted signal, linear power amplifiers (class A, B, or AB) are usually used as a solution for the power amplifier stage. These amplifiers have high linearity, but suffer from low efficiency when the transmitted signal has high peak-to-average power ratio. The Kahn envelope elimination and restoration technique is used to enhance the efficiency of RF transmitters, by combining highly efficient, nonlinear RF amplifier (class E) with a highly efficient envelope amplifier in order to obtain a linear and highly efficient RF amplifier. This paper presents a solution for the envelope amplifier based on a multilevel converter in series with a linear regulator. The multilevel converter is implemented by employing voltage dividers based on switching capacitors. The implemented envelope amplifier can reproduce any signal with a maximum spectral component of 2 MHz and give instantaneous maximum power of 50 W. The efficiency measurements show that when the signals with low average value are transmitted, the implemented prototypes have up to 20% higher efficiency than linear regulators used as a conventional solution.

Survey of architectures and optimizations for wide bandwidth envelope amplifier

In the last years, RF power amplifiers are taking advantage of the switched dc-dc converters to use them in several architectures that may improve the efficiency of the amplifier, keeping a good linearity. The use of linearization techniques such as Envelope Elimination and Restoration(EER) and Envelope Tracking (ET) requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier but theoretically the efficiency can be much higher than using the classical amplifiers belonging to classes A, B or AB. The purpose of this paper is to analyze the state of the art of the power converters used as envelope amplifiers in this application. The power topologies will be explored and several important parameters such as efficiency, bandwidth will be discussed.

High Efficiency Envelope Amplifier Using The Slow-Envelope Technique

High efficiency envelope amplifiers are demanded in EER technique for RF transmitters, which benefits low maintaining cost or long battery time. The conventional solution is a dc-dc switching converters. This dc-dc converter should operate at very high frequency to track an envelope in the MHz range to supply the power amplifier. One of the alternative circuits suitable for this application is a hybrid topology composed of a switched converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. This topology can take advantage of the reduced slew-rate technique (also called slow-envelope technique) where switching dc-dc converter provides the RF envelope with limited slew rate in order to avoid high switching frequency and high power losses, while the linear regulator performs fine adjustment in order to obtain the exact replica of the RF envelope. The combination of this control technique with this topology is proposed in this paper. Envelopes with different bandwidth will be considered to optimize the efficiency of the dc-dc converter.

Envelope Amplifier Based on a Hybrid Series Converter With The Slow-envelope Technique

High frequency dc-dc switching converters are used as envelope amplifiers in RF transmitters. The dc-dc converter should operate at very high frequency to track an envelope in the MHz range to supply the power amplifier. One of the circuits suitable for this application is a hybrid topology composed of a switched converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. This topology can take advantage of the reduced slew-rate technique where switching dc-dc converter provides the RF envelope with limited slew rate in order to avoid high switching frequency and high power losses, while the linear regulator performs fine adjustment in order to obtain the exact replica of the RF envelope. The combination of this control technique with this topology is proposed in this paper. Envelopes with different bandwidth will be considered to optimize the efficiency of the dc-dc converter. The calculations and experiments have been done to track a 2MHz envelope in the range 0-12V for an EER RF transmitter.

An overview of fast DC-DC converters for envelope amplifier in RF transmitters

In the last years, RF power amplifiers are taking advantage of the switched dc-dc converters to use them in several architectures that may improve the efficiency of the amplifier, keeping a good linearity. The use of linearization techniques such as Envelope Elimination and Restoration (EER) and Envelope Tracking (ET) requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier but theoretically the efficiency can be much higher than using the classical amplifiers belonging to classes A, B or AB. The purpose of this paper is to analyze the state of the art of the power converters used as envelope amplifiers in this application where a fast output voltage variation is required. The power topologies will be explored and several important parameters such as efficiency, bandwidth and output voltage range will be discussed.