A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-Level Inverter for The Full Modulation Range

A switched DC voltage three level NPC is proposed in this paper to eliminate capacitor balancing problems in conventional three-level Neutral Point Clamped (NPC) inverter. The proposed configuration requires only one DC link with a voltage V-dc/2, where V-dc is the DC link voltage in a onventional NPC inverter. To get rated DC link voltage (V-dc), the voltage source is alternately onnected in parallel to one of the two series capacitors using two switches and two diodes with device voltage rating of V-dc/2. The frequency at which the voltage source is switched is independent and will not affect the operation of NPC inverter. The switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two level inverter in lower modulation range, thereby increases the reliability of the drive system. A space vector based PWM scheme is used to verify this proposed topology.

Development of a multi-locus sequence typing scheme for avian isolates of Pasteurella multocida.

A total of 63 isolates of Pasteurella multocida from Australian poultry, all associated with fowl cholera outbreaks, and three international reference strains, representing the three subspecies within P. multocida were used to develop a multi-locus sequence typing scheme. Primers were designed for conserved regions of seven house-keeping enzymes - adk, est, gdh, mdh, pgi, pmi and zwf - and internal fragments of 570-784 bp were sequenced for all isolates and strains. The number of alleles at the different loci ranged from 11 to 20 and a total of 29 allelic profiles or sequence types were recognised amongst the 66 strains. There was a strong concordance between the MLST data and the existing multi-locus enzyme electrophoresis and ribotyping data. When used to study a sub-set of isolates with a known detailed epidemiological history, the MLST data matched the results given by restriction endonuclease analysis, pulsed-field gel electrophoresis, ribotyping and REP-PCR. The MLST scheme provides a high level of resolution and is an excellent tool for studying the population structure and epidemiology of P. multocida.

Levels and predictors of exercise referral scheme uptake and adherence: A systematic review

Background The effectiveness of exercise referral schemes (ERS) is influenced by uptake and adherence to the scheme. The identification of factors influencing low uptake and adherence could lead to the refinement of schemes to optimise investment. Objectives To quantify the levels of ERS uptake and adherence and to identify factors predictive of uptake and adherence. Methods A systematic review and meta-analysis was undertaken. MEDLINE, EMBASE, PsycINFO, Cochrane Library, ISI WOS, SPORTDiscus and ongoing trial registries were searched (to October 2009) and included study references were checked. Included studies were required to report at least one of the following: (1) a numerical measure of ERS uptake or adherence and (2) an estimate of the statistical association between participant demographic or psychosocial factors (eg, level of motivation, self-efficacy) or programme factors and uptake or adherence to ERS. Results Twenty studies met the inclusion criteria, six randomised controlled trials (RCTs) and 14 observational studies. The pooled level of uptake in ERS was 66% (95% CI 57% to 75%) across the observational studies and 81% (95% CI 68% to 94%) across the RCTs. The pooled level of ERS adherence was 49% (95% CI 40% to 59%) across the observational studies and 43% (95% CI 32% to 54%) across the RCTs. Few studies considered anything other than gender and age. Women were more likely to begin an ERS but were less likely to adhere to it than men. Older people were more likely to begin and adhere to an ERS. Limitations Substantial heterogeneity was evident across the ERS studies. Without standardised definitions, the heterogeneity may have been reflective of differences in methods of defining uptake and adherence across studies. Conclusions To enhance our understanding of the variation in uptake and adherence across ERS and how these variations might affect physical activity outcomes, future trials need to use quantitative and qualitative methods.

Random security scheme selection for mobile transactions

Security in a mobile communication environment is always a matter for concern, even after deploying many security techniques at device, network, and application levels. The end-to-end security for mobile applications can be made robust by developing dynamic schemes at application level which makes use of the existing security techniques varying in terms of space, time, and attacks complexities. In this paper we present a security techniques selection scheme for mobile transactions, called the Transactions-Based Security Scheme (TBSS). The TBSS uses intelligence to study, and analyzes the security implications of transactions under execution based on certain criterion such as user behaviors, transaction sensitivity levels, and credibility factors computed over the previous transactions by the users, network vulnerability, and device characteristics. The TBSS identifies a suitable level of security techniques from the repository, which consists of symmetric, and asymmetric types of security algorithms arranged in three complexity levels, covering various encryption/decryption techniques, digital signature schemes, andhashing techniques. From this identified level, one of the techniques is deployed randomly. The results shows that, there is a considerable reduction in security cost compared to static schemes, which employ pre-fixed security techniques to secure the transactions data.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulationn range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drivesystem. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

Investigating the interactions of road users and pedestrians in a dynamic rail level crossing environment

There are 23,500 level crossings in Australia. In these types of environments it is important to understand what human factor issues are present and how road users and pedestrians engage with crossings. A series of on-site observations were performed over a 2-day period at a 3-track active crossing. This was followed by 52 interviews with local business owners and members of the public. Data were captured using a manual-coding scheme for recording and categorising violations. Over 700 separate road user and pedestrian violations were recorded, with representations in multiple categories. Time stamping revealed that the crossing was active for 59% of the time in some morning periods. Further, trains could take up to 4-min to arrive following its first activation. Many pedestrians jaywalked under side rails and around active boom gates. In numerous cases pedestrians put themselves at risk in order to beat or catch the approaching train, ignored signs to stop walking when the lights were flashing. Analysis of interview data identified themes associated with congestion, safety, and violations. This work offers insight into context specific issues associated with active level crossing protection.

An SIMD machine for low-level vision

This paper presents an SIMD machine which has been tuned to execute low-level vision algorithms employing the relaxation labeling paradigm. Novel features of the design include: 1. (1) a communication scheme capable of window accessing under a single instruction. 2. (2) flexible I/O instructions to load overlapped data segments; and 3. (3) data-conditional instructions which can be nested to an arbitrary degree. A time analysis of the stereo correspondence problem, as implemented on a simulated version of the machine using the probabilistic relaxation technique, shows a speed up of almost N2 for an N × N array of PEs.

A Simple Five-Level Inverter Topology for Induction Motor Drive Using Conventional Two-Level Inverters and Flying Capacitor Technique

This paper proposes a new five-level inverter topology for open-end winding induction motor (IM) drive. The popular existing circuit configurations for five-level inverter include the NPC inverter and flying capacitor topologies. Compared to the NPC inverter, the proposed topology eliminates eighteen clamping diodes having different voltage ratings in the present circuit. Moreover it requires only one capacitor bank per phase, whereas flying capacitor schemes for five level topologies require six capacitor banks per phase. The proposed topology is realized by feeding the phase winding of an open-end induction motor with two-level inverters in series with flying capacitors. The flying capacitor voltages are balanced using the switching state redundancy for full modulation range. The proposed inverter scheme is capable of producing two-level to five-level pulse width modulated voltage across the phase winding depending on the modulation range. Additionally, in case of any switch failure in the flying capacitor connection, the proposed inverter topology can be operated as a three-level inverter for full modulation range. The proposed scheme is experimentally verified on a four pole, 5hp induction motor drive.

A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using Two-Level Inverters in Series With a Capacitor-Fed H-Bridge Cell

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

Performance Analysis of User Selected Subband Channel Quality Indicator Feedback Scheme of LTE

Frequency-domain scheduling and rate adaptation have helped next generation orthogonal frequency division multiple access (OFDMA) based wireless cellular systems such as Long Term Evolution (LTE) achieve significantly higher spectral efficiencies. To overcome the severe uplink feedback bandwidth constraints, LTE uses several techniques to reduce the feedback required by a frequency-domain scheduler about the channel state information of all subcarriers of all users. In this paper, we analyze the throughput achieved by the User Selected Subband feedback scheme of LTE. In it, a user feeds back only the indices of the best M subbands and a single 4-bit estimate of the average rate achievable over all selected M subbands. In addition, we compare the performance with the subband-level feedback scheme of LTE, and highlight the role of the scheduler by comparing the performances of the unfair greedy scheduler and the proportional fair (PF) scheduler. Our analysis sheds several insights into the working of the feedback reduction techniques used in LTE.

Investigation on the Potential Rise and Currents in Insulated Mast Scheme with Single Tower During Stroke Interception

The insulated mast scheme for the lightning protection system can be found in a few practical designs. Many advantages over conventional protection system are some times envisaged. However, the technical literature on the analysis of such schemes and further quantification of their protection efficacy is rather scarce. As a first step to address this problem, the present work is taken up and the potential rise at the top and ground end currents in insulating mast scheme with single tower is investigated for several tower heights and pertinent values of other parameters. The quantities that are investigated are the potential difference across the insulation and ground end currents for both tower and the ground wires. Quantifications are carried out for the relevant range of stroke current front times. The influence of number of ground wires, their earthing location and to a limited extent, the length of the insulating support have been ascertained. Some relevant discussion on insulation strength is made. These findings are quite novel and aid in quantification of the practical efficacy of the insulated mast scheme. The level of induction to the support tower and possible flashover to the same are not in favour of this scheme.

Two-level Mapping Based Cache Index Selection for Packet Forwarding Engines

Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the placement function to reduce conflict misses. Traditional placement functions use a one-level mapping that naively partitions trie-nodes into cache sets. However, as a significant percentage of trie nodes are not useful, these schemes suffer from a non-uniform distribution of useful nodes to sets. This in turn results in increased conflict misses. Newer organizations such as variable associativity caches achieve flexibility in placement at the expense of increased hit-latency. This makes them unsuitable for L1 caches.We propose a novel two-level mapping framework that retains the hit-latency of one-level mapping yet incurs fewer conflict misses. This is achieved by introducing a secondlevel mapping which reorganizes the nodes in the naive initial partitions into refined partitions with near-uniform distribution of nodes. Further as this remapping is accomplished by simply adapting the index bits to a given routing table the hit-latency is not affected. We propose three new schemes which result in up to 16% reduction in the number of misses and 13% speedup in memory access time. In comparison, an XOR-based placement scheme known to perform extremely well for general purpose architectures, can obtain up to 2% speedup in memory access time.

Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory

Software transactional memory (STM) has been proposed as a promising programming paradigm for shared memory multi-threaded programs as an alternative to conventional lock based synchronization primitives. Typical STM implementations employ a conflict detection scheme, which works with uniform access granularity, tracking shared data accesses either at word/cache line or at object level. It is well known that a single fixed access tracking granularity cannot meet the conflicting goals of reducing false conflicts without impacting concurrency adversely. A fine grained granularity while improving concurrency can have an adverse impact on performance due to lock aliasing, lock validation overheads, and additional cache pressure. On the other hand, a coarse grained granularity can impact performance due to reduced concurrency. Thus, in general, a fixed or uniform granularity access tracking (UGAT) scheme is application-unaware and rarely matches the access patterns of individual application or parts of an application, leading to sub-optimal performance for different parts of the application(s). In order to mitigate the disadvantages associated with UGAT scheme, we propose a Variable Granularity Access Tracking (VGAT) scheme in this paper. We propose a compiler based approach wherein the compiler uses inter-procedural whole program static analysis to select the access tracking granularity for different shared data structures of the application based on the application's data access pattern. We describe our prototype VGAT scheme, using TL2 as our STM implementation. Our experimental results reveal that VGAT-STM scheme can improve the application performance of STAMP benchmarks from 1.87% to up to 21.2%.

Five-level inverter voltage-space phasor generation for an open-end winding induction motor drive

A topology for voltage-space phasor generation equivalent to a five-level inverter for an open-end winding induction motor is presented. The open-end winding induction motor is fed from both ends by two three-level inverters. The three-level inverters are realised by cascading two two-level inverters. This inverter scheme does not experience neutral-point fluctuations. Of the two three-level inverters only one will be switching at any instant in the lower speed ranges. In the multilevel carrier-based SPWM used for the proposed drive, a progressive discrete DC bias depending on the speed range is given to the reference wave to reduce the inverter switchings. The drive is implemented and tested with a 1 HP open-end winding induction motor and experimental results are presented.