Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Effect of Pt doping on the gas sensing properties of porous chromium oxide films through a kinetic response analysis approach

The effect of doping trace amounts of noblemetals (Pt) on the gas sensing properties of chromium oxide thin films, is studied. The sensors are fabricated by depositing chromium oxide films on a glass substrate using a modified spray pyrolysis technique and characterized using X-ray diffraction, scanning electron microscopy, transmission electron microscopy and X-ray photoelectron spectroscopy. The films are porous and nanocrystalline with an average crystallite size of similar to 30 nm. The typical p-type conductivity arises due to the presence of Cr vacancies, formed as a result of Cr non-stoichiometry, which is found to vary upon Pt doping. In order to analyze the effect of doping on the gas sensing properties, we have adopted a kinetic response analysis approach, which is based on Langmuir Adsorption isotherm (LA) theory. The sensor response is analyzed with equations obtained from LA theory and time constants as well as energies of adsorption-desorption are evaluated. It is seen that, Pt doping lowers the Schottky barrier height of the metal oxide semiconductor sensor from 222 meV to 172 meV. Subsequently the reduction in adsorption and desorption energies led to enhancement in sensor response and improvement in the kinetics of the sensor response i.e. the response time as well as recovery times of the sensor.

A high temperature SOI CMOS NO2 sensor

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors. © 2011 American Institute of Physics.

Gated three-terminal device architecture to eliminate persistent photoconductivity in oxide semiconductor photosensor arrays

The composition of amorphous oxide semiconductors, which are well known for their optical transparency, can be tailored to enhance their absorption and induce photoconductivity for irradiation with green, and shorter wavelength light. In principle, amorphous oxide semiconductor-based thin-film photoconductors could hence be applied as photosensors. However, their photoconductivity persists for hours after illumination has been removed, which severely degrades the response time and the frame rate of oxide-based sensor arrays. We have solved the problem of persistent photoconductivity (PPC) by developing a gated amorphous oxide semiconductor photo thin-film transistor (photo-TFT) that can provide direct control over the position of the Fermi level in the active layer. Applying a short-duration (10 ns) voltage pulse to these devices induces electron accumulation and accelerates their recombination with ionized oxygen vacancy sites, which are thought to cause PPC. We have integrated these photo-TFTs in a transparent active-matrix photosensor array that can be operated at high frame rates and that has potential applications in contact-free interactive displays. © 2012 Macmillan Publishers Limited. All rights reserved.

Amorphous oxide semiconductor TFTs for displays and imaging

© 2013 IEEE. This paper reviews the mechanisms underlying visible light detection based on phototransistors fabricated using amorphous oxide semiconductor technology. Although this family of materials is perceived to be optically transparent, the presence of oxygen deficiency defects, such as vacancies, located at subgap states, and their ionization under illumination, gives rise to absorption of blue and green photons. At higher energies, we have the usual band-to-band absorption. In particular, the oxygen defects remain ionized even after illumination ceases, leading to persistent photoconductivity, which can limit the frame-rate of active matrix imaging arrays. However, the persistence in photoconductivity can be overcome through deployment of a gate pulsing scheme enabling realistic frame rates for advanced applications such as sensor-embedded display for touch-free interaction.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

Metal oxide photoanodes for solar hydrogen production

The development of sustainable hydrogen production is a key target in the further facilitation of a hydrogen economy. Solar hydrogen generation through the photolytic splitting of water sensitised by semiconductor materials is attractive as it is both renewable and does not lead to problematic by-products, unlike current hydrogen sources such as natural gas. Consequently, the development of these semiconductor materials has undergone considerable research since their discovery over 30 years ago and it would seem prescient to review the more practical results of this research. Among the critical factors influencing the choice of semiconductor material for photoelectrolysis of water are the band-gap energies, flat band potentials and stability towards photocorrosion; the latter of these points directs us to focus on metal oxides. Careful design of thin films of photocatalyst material can eliminate potential routes of losses in performance, i.e., recombination at grain boundaries. Methods to overcome these problems are discussed such as coupling a photoanode for photolysis of water to a photovoltaic cell in a 'tandem cell' device.

Freestanding polymer-metal oxide nanocomposite films for light-driven oxygen scavenging

Freestanding films containing nanocrystalline TiO2 and a suitable electron donor embedded in a cellulose matrix deoxygenate a closed environment (see Figure) upon UV illumination as a result of the photocatalytic properties of TiO2. This opens up the potential use of semiconductor photocatalysis in active packaging to achieve light-driven deoxygenation of closed environments.

Nonaqueous sol-gel routes to doped metal oxide nanoparticles: synthesis, characterization, assembly and properties

The results presented in this thesis have been achieved under the Ph.D. project entitled “Nonaqueous Sol-Gel routes to doped metal oxide nanoparticles: Synthesis, characterization, assembly and properties”. The purpose of this study is the investigation of metal oxide nanostructures doped with metals of a diverse nature, leading to different type of applications. The easier control over the reaction kinetics in solvothermal routes, compared to aqueous methods, allows to better match the reactivity between metal oxide precursors, paving the way to a facile and low temperature production of doped oxides. In this manuscript diverse examples of the exploitation of the “Benzyl Alcohol Route” are discussed. Such a powerful pathway was utilized for the synthesis of transition metal doped zirconia, hafnia and various perovskites, and the study of their magnetic properties, as well as the synthesis of rare earth doped zirconium oxide. A further extension, proving the solidity of the synthetic method, is shown for the preparation of Li4Ti5O12 nanocrystals carrying excellent electrochemical properties for lithium-ion battery applications. Finally, the effect of doping and other reaction parameters on the assembly of the nanocrystals is discussed. These studies were carried out principally at the University of Aveiro, as well as at the University of Montpellier II and at the Seoul National University due to complementary available expertises and equipments.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Negative temperature coefficient thermistor based on Bi3Zn2Sb3O14 ceramic: An oxide semiconductor at high temperature

Bi1.5ZnSb1.5O7 dielectric ceramic with pyrochlore structure was investigated by impedance spectroscopy from 400 to 750 degreesC. Pyrochlore was synthesized by the polymeric precursor method, a chemical synthesis route derived from Pechini's method. The grain or bulk resistance exhibits a sensor temperature characteristic, being a thermistor with a negative temperature coefficient (NTC). Only a single region was identified on the resistance curve investigated. The NTC thermistor characteristic parameter (beta) is equal to 7140 degreesC, in the temperature range investigated. The temperature coefficient of the resistance (alpha) was derived, being equal to -4.46x10(-2) degreesC(-1) at 400 degreesC. The conduction mechanism and relaxation are discussed. (C) 2003 American Institute of Physics.

Theory of electrical characteristics for metal-oxide-insulator Schottky barrier and metal-insulator-metal structures

The metal-insulator or metal-amorphous semiconductor blocking contact is still not well understood. Here, the intimate metal-insulator and metal-oxide-insulator contact are discussed. Further, the steady-state characteristics of metal-oxide-insulator-metal structures are also discussed. Oxide is an insulator with wider energy band gap (about 50 Å thick). A uniform energetic distribution of impurities is considered in addition to impurities at a single energy level inside the surface charge region at the oxide-insulator interface. Analytical expressions are presented for electrical potential, field, thickness of the depletion region, capacitance, and charge accumulated in the surface charge region. The electrical characteristics are compared with reference to relative densities of two types of impurities. ln I is proportional to the square root of applied potential if energetically distributed impurities are relatively important. However, distribution of the electrical potential is quite complicated. In general energetically distributed impurities can considerably change the electrical characteristics of these structures.

Design principles for maximizing photovoltage in metal-oxide-protected water-splitting photoanodes

Metal oxide protection layers for photoanodes may enable the development of large-scale solar fuel and solar chemical synthesis, but the poor photovoltages often reported so far will severely limit their performance. Here we report a novel observation of photovoltage loss associated with a charge extraction barrier imposed by the protection layer, and, by eliminating it, achieve photovoltages as high as 630mV, the maximum reported so far for water-splitting silicon photoanodes. The loss mechanism is systematically probed in metal-insulator-semiconductor Schottky junction cells compared to buried junction p(+) n cells, revealing the need to maintain a characteristic hole density at the semiconductor/insulator interface. A leaky-capacitor model related to the dielectric properties of the protective oxide explains this loss, achieving excellent agreement with the data. From these findings, we formulate design principles for simultaneous optimization of built-in field, interface quality, and hole extraction to maximize the photovoltage of oxide-protected water-splitting anodes.

Engineering interfacial silicon dioxide for improved metal-insulator-semiconductor silicon photoanode water splitting performance

Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.