Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.

CORDIC based application-specific instruction set processor for QRD/SVD

An application specific programmable processor (ASIP) suitable for the real-time implementation of matrix computations such as Singular Value and QR Decomposition is presented. The processor incorporates facilities for the issue of parallel instructions and a dual-bus architecture that are designed to achieve high performance. Internally, it uses a CORDIC module to perform arithmetic operations, with pipelining of the internal recursive loop exploited to multiplex the two independent micro-rotations onto a single piece of hardware. The net result is a flexible processing element whose functionality can be changed under program control, which combines high performance with efficient silicon implementation. This is illustrated through the results of a detailed silicon design study and the applications of the techniques to a combined SVD/QRD system.

Managing SMT Resource Usage through Speculative Instruction Window Weighting

Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, for instance, by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly; that is, resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions.

Fetch Gating Control through Speculative Instruction Window Weighting

In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. Till recently, the front-end was designed to maximize performance without considering energy consumption. The front-end fetches instructions as fast as it can until it is stalled by a filled issue queue or some other blocking structure. This approach wastes energy: (i) speculative execution causes many wrong-path instructions to be fetched and executed, and (ii) back-end execution rate is usually less than its peak rate, but front-end structures are dimensioned to sustained peak performance. Dynamically reducing the front-end instruction rate and the active size of front-end structure (e.g. issue queue) is a required performance-energy trade-off. Techniques proposed in the literature attack only one of these effects.
In previous work, we have proposed Speculative Instruction Window Weighting (SIWW) [21], a fetch gating technique that allows to address both fetch gating and instruction issue queue dynamic sizing. SIWW computes a global weight on the set of inflight instructions. This weight depends on the number and types of inflight instructions (non-branches, high confidence or low confidence branches, ...). The front-end instruction rate can be continuously adapted based on this weight. This paper extends the analysis of SIWW performed in previous work. It shows that SIWW performs better than previously proposed fetch gating techniques and that SIWW allows to dynamically adapt the size of the active instruction queue.

Methods for Optimal Work Instruction Delivery: Pictograms v Images

This paper focuses on quantifying the benefits of pictogram based instructions relative to static images for work instruction delivery. The assembly of a stiffened aircraft panel has been used as an exemplar for the work which seeks to address the challenge of identifying an instructional mode that can be location or language neutral while at the same time optimising assembly build times and maintaining build quality. Key performance parameters measured using a series of panel build experiments conducted by two separate groups were: overall build time, the number of subject references to instructional media, the number of build errors and the time taken to correct any mistakes. Overall build time for five builds for a group using pictogram instructions was about 20% lower than for the group using image based instructions. Also, the pictogram group made fewer errors. Although previous work identified that animated instructions result in optimal build times, the language neutrality of pictograms as well as the fact that they can be used without visualisation hardware mean that, on balance, they have broader applicability in terms of transferring assembly knowledge to the manufacturing environment.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

Who gets to play? Investigating equity in musical instrument instruction in Scottish primary schools

There is a widely held view that learning to play a musical instrument is a valuable experience for all children in terms of their personal growth and development. Although there is no statutory obligation for instrumental music provision in Scottish primary schools, there are well-established Instrumental Music Services in Local Education Authorities that have been developed to provide this facility for pupils. This article presents the findings of a study that was aimed at investigating the extent to which the opportunity to undertake instrumental instruction in Scottish primary schools is equitable. The study employed a mixed-methods approach. Data were gathered from 21 Scottish primary schools, a total pupil population of 5122 pupils of whom 323 pupils were receiving instrumental instruction. The analysis involved an investigation of the academic profile of this group, the representation of children with additional support needs (ASN) and the nature of their ASN. A qualitative analysis of policy and guideline documents and interviews with Heads of Instrumental Services, headteachers and instrumental instructors served to explain and illuminate the quantitative data. The findings showed that particular groups of children with ASN were significantly under-represented and offer explanations of the processes by which this occurs.

Réunion des sociétés savantes des départements à la Sorbonne.... Section des beaux-arts / Ministère de l'instruction publique...

1905 (SESSION29).

Réunion des sociétés savantes des départements à la Sorbonne.... Section des beaux-arts / Ministère de l'instruction publique...

1878.

Réunion des sociétés savantes des départements à la Sorbonne.... Section des beaux-arts / Ministère de l'instruction publique...

1901 (SESSION25).

Réunion des sociétés savantes des départements à la Sorbonne.... Section des beaux-arts / Ministère de l'instruction publique...

1899 (SESSION23).