FPGA-based object detection using classification circuits

Dans l'apprentissage machine, la classification est le processus d’assigner une nouvelle observation à une certaine catégorie. Les classifieurs qui mettent en œuvre des algorithmes de classification ont été largement étudié au cours des dernières décennies. Les classifieurs traditionnels sont basés sur des algorithmes tels que le SVM et les réseaux de neurones, et sont généralement exécutés par des logiciels sur CPUs qui fait que le système souffre d’un manque de performance et d’une forte consommation d'énergie. Bien que les GPUs puissent être utilisés pour accélérer le calcul de certains classifieurs, leur grande consommation de puissance empêche la technologie d'être mise en œuvre sur des appareils portables tels que les systèmes embarqués. Pour rendre le système de classification plus léger, les classifieurs devraient être capable de fonctionner sur un système matériel plus compact au lieu d'un groupe de CPUs ou GPUs, et les classifieurs eux-mêmes devraient être optimisés pour ce matériel. Dans ce mémoire, nous explorons la mise en œuvre d'un classifieur novateur sur une plate-forme matérielle à base de FPGA. Le classifieur, conçu par Alain Tapp (Université de Montréal), est basé sur une grande quantité de tables de recherche qui forment des circuits arborescents qui effectuent les tâches de classification. Le FPGA semble être un élément fait sur mesure pour mettre en œuvre ce classifieur avec ses riches ressources de tables de recherche et l'architecture à parallélisme élevé. Notre travail montre que les FPGAs peuvent implémenter plusieurs classifieurs et faire les classification sur des images haute définition à une vitesse très élevée.

Synthesis, Characterisation and Properties of (Ba1-xSrx) (Nd1/2Nb1/2 ) 03 Ceramics for Application as Dielectric Resonators in Microwave Circuits

The (Ba1-x Srx) (Nd1/2, Nb1/2) O3 ceramics have been prepared by the conventional ceramic route for different values of x. Addition of a small amount of CeO2(1 wt%) as a sintering aid increased the density of the samples. The structure and microstructure of the sintered samples are studied by X-ray diffraction and SEM methods. The dielectric properties of the samples are measured in the microwave frequency region as a function of composition. The dielectric constant decreases as x increases. The coefficient of thermal variation of resonant frequency decreases as the Sr content increases and goes to the negative side. The dielectric properties of (Ba1-x Srx) (Nd1/2, Nb1/2) O3 are in the range suitable for application as dielectric resonators in microwave circuits

A Faster 2D Technique for the design of Combinational Digital Circuits Using Genetic Algorithm

Combinational digital circuits can be evolved automatically using Genetic Algorithms (GA). Until recently this technique used linear chromosomes and and one dimensional crossover and mutation operators. In this paper, a new method for representing combinational digital circuits as 2 Dimensional (2D) chromosomes and suitable 2D crossover and mutation techniques has been proposed. By using this method, the convergence speed of GA can be increased significantly compared to the conventional methods. Moreover, the 2D representation and crossover operation provides the designer with better visualization of the evolved circuits. In addition to this, a technique to display automatically the evolved circuits has been developed with the help of MATLAB

An Improved Design of Combinational Digital Circuits with Multiplexers using Genetic Algorithm

This paper presents a new approach to the design of combinational digital circuits with multiplexers using Evolutionary techniques. Genetic Algorithm (GA) is used as the optimization tool. Several circuits are synthesized with this method and compared with two design techniques such as standard implementation of logic functions using multiplexers and implementation using Shannon’s decomposition technique using GA. With the proposed method complexity of the circuit and the associated delay can be reduced significantly

Formal Multilevel Hierarchical Verification of Synchronous MOS Circuits

I have designed and implemented a system for the multilevel verification of synchronous MOS VLSI circuits. The system, called Silica Pithecus, accepts the schematic of an MOS circuit and a specification of the circuit's intended digital behavior. Silica Pithecus determines if the circuit meets its specification. If the circuit fails to meet its specification Silica Pithecus returns to the designer the reason for the failure. Unlike earlier verifiers which modelled primitives (e.g., transistors) as unidirectional digital devices, Silica Pithecus models primitives more realistically. Transistors are modelled as bidirectional devices of varying resistances, and nodes are modelled as capacitors. Silica Pithecus operates hierarchically, interactively, and incrementally. Major contributions of this research include a formal understanding of the relationship between different behavioral descriptions (e.g., signal, boolean, and arithmetic descriptions) of the same device, and a formalization of the relationship between the structure, behavior, and context of device. Given these formal structures my methods find sufficient conditions on the inputs of circuits which guarantee the correct operation of the circuit in the desired descriptive domain. These methods are algorithmic and complete. They also handle complex phenomena such as races and charge sharing. Informal notions such as races and hazards are shown to be derivable from the correctness conditions used by my methods.

Taming Chaotic Circuits

Control algorithms that exploit chaotic behavior can vastly improve the performance of many practical and useful systems. The program Perfect Moment is built around a collection of such techniques. It autonomously explores a dynamical system's behavior, using rules embodying theorems and definitions from nonlinear dynamics to zero in on interesting and useful parameter ranges and state-space regions. It then constructs a reference trajectory based on that information and causes the system to follow it. This program and its results are illustrated with several examples, among them the phase-locked loop, where sections of chaotic attractors are used to increase the capture range of the circuit.

Biologically Plausible Neural Circuits for Realization of Maximum Operations

Object recognition in the visual cortex is based on a hierarchical architecture, in which specialized brain regions along the ventral pathway extract object features of increasing levels of complexity, accompanied by greater invariance in stimulus size, position, and orientation. Recent theoretical studies postulate a non-linear pooling function, such as the maximum (MAX) operation could be fundamental in achieving such invariance. In this paper, we are concerned with neurally plausible mechanisms that may be involved in realizing the MAX operation. Four canonical circuits are proposed, each based on neural mechanisms that have been previously discussed in the context of cortical processing. Through simulations and mathematical analysis, we examine the relative performance and robustness of these mechanisms. We derive experimentally verifiable predictions for each circuit and discuss their respective physiological considerations.

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

Professionals: L'experiència d'un titulat que desenvolupa la seva activitat professional dissenyant circuits electrònics

Seguint amb l’objectiu que titulats a l’Escola Politècnica Superior expliquin detalls de la seva inserció laboral i del seu perfil professional, en aquest segon número de la revista entrevistem el Sr. Albert Pijuan Vila. En aquest cas no es tracta d’un titulat recent, ja que l’Albert va finalitzar els estudis l’any 1988. Recordem que, si bé al 1988 ja disposàvem de d’actual edifici P-I de l’EPS, l’escola encara estava vinculada a la Universitat Politècnica de Catalunya. El principal interès que ens ha mogut a entrevistar l’Albert ha estat el fet de poder presentar les característiques d’un tipus de lloc de treball que pot ser adient per a alguns dels titulats actuals de l’EPS, especialment d’Enginyeria Tècnica Industrial, especialitat Electrònica Industrial i Enginyeria Tècnica en Informàtica de Sistemes. L’entrevista també vol explorar quins són els tipus de coneixements i les competències que haurien d’adquirir els estudiants per adequar-se millor a aquest tipus de sortida professional

Labor's shares - aggregate and industry: accounting for both in a model of unbalanced growth with induced innovation

The relative stability of aggregate labor's share constitutes one of the great macroeconomic ratios. However, relative stability at the aggregate level masks the unbalanced nature of industry labor's shares – the Kuznets stylized facts underlie those of Kaldor. We present a two-sector – one labor-only and the other using both capital and labor – model of unbalanced economic development with induced innovation that can rationalize these phenomena as well as several other empirical regularities of actual economies. Specifically, the model features (i) one sector ("goods" production) becoming increasingly capital-intensive over time; (ii) an increasing relative price and share in total output of the labor-only sector ("services"); and (iii) diverging sectoral labor's shares despite (iii) an aggregate labor's share that converges from above to a value between 0 and unity. Furthermore, the model (iv) supports either a neoclassical steadystate or long-run endogenous growth, giving it the potential to account for a wide range of real world development experiences.

Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients. Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació. Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge. En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.

Evaluating the performance of external fault ridethrough solutions used in wind farms with fixed speed induction generators when facing unbalanced faults

Na sequência da integração da energia eólica em larga escala foram estabelecidos códigos de rede pelos vários operadores de sistema, exigindo que os parques eólicos permaneçam em serviço durante e após a ocorrência de defeitos na rede a montante. Nos parques eólicos equipados com sistemas de velocidade constante este requisito pode ser assegurado pela instalação, no ponto de interligação à rede, de equipamento de compensação dinâmica de potência reactiva, controlado como fonte de tensão, sendo as funções de controlo baseadas em medidas efectuadas no ponto de interligação relativamente às componentes directas da tensão e da corrente. Como a adopção deste tipo de soluções externas é adequada ao funcionamento do sistema em regime equilibrado, este artigo foca a avaliação do desempenho da solução no caso da ocorrência de defeitos assimétricos. Os resultados obtidos através das simulações dinâmicas evidenciam o aparecimento de sobre tensões nas fases não afectadas pelo defeito que poderão colocar o parque eólico fora de serviço.