994 resultados para Semiconductor films


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Mechanical properties of thin films such as residual stress and hardness are of paramount importance from the device fabrication point of view. Intrinsic stress in sputtered films can be tensile or compressive as decided by the number density and the energy of the plasma species striking the growing film. In the presence of hydrogen we analyzed the applicability of idealized stress reversal curve for amorphous silicon thin films deposited by DC, pulsed DC (PDC) and RF sputtering. We are successfully able to correlate the microstructure with the stress reversal and hardness. We observed a stress reversal from compressive to tensile with hydrogen incorporation. It was found that unlike in idealized stress reversal curve case, though the energy of plasma species is less in DC plasma, DC deposited films exhibit more compressive stress, followed by PDC and RF deposited films. A tendency towards tensile stress from compressive stress was observed at similar to 13, 18 and 23 at%H for DC, PDC and RF deposited films respectively, which is in exact agreement with the vacancy to void transition in the films. Regardless of the sputtering power mode, the hardness of a-Si:H films is found to be maximum at C-H similar to 10 at%H. Enhancement in hardness with C-H (up to C-H similar to 10 at%H) is attributed to increase of Si-H bonds. Beyond C-H similar to 10 at%H, hardness starts falling. (C) 2015 Elsevier Ltd. All rights reserved.

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Titanium dioxide thin films were deposited by RF reactive magnetron sputtering technique on p-type silicon(100) substrates held at temperatures in the range 303-673 K. The influence of substrate temperature on the core level binding energies, chemical bonding configuration, crystallographic structure and dielectric properties was investigated. X-ray photoelectron spectroscopy studies and Fourier transform infrared transmittance data confirmed the formation of stoichiometric films with anatase phase at a substrate temperature of 673 K. The films formed at 303 K were nanocrystalline with amorphous matrix while those deposited at 673 K were transformed in to crystalline phase and growth of grains in pyramidal like structure as confirmed by X-ray diffraction and atomic force microscopy respectively. Metal-oxide-semiconductor capacitors were fabricated with the configuration of Al/TiO2/Si structures. The current voltage, capacitance voltage and conductance voltage characteristics were studied to understand the electrical conduction and dielectric properties of the MOS devices. The leakage current density (at gate voltage of 2 V) decreased from 2.2 x 10(-6) to 1.7 x 10(-7) A/cm(2), the interface trap density decreased from 1.2 x 10(13) to 2.1 x 10(12) cm(-2) eV(-1) and the dielectric constant increased from 14 to 36 with increase of substrate temperature from 303 to 673 K.

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Cu(In,Al)Se-2 films are grown using single step electrodeposition technique. The film properties are studied by varying the deposition time from 500 to 2000 s. Peaks corresponding to elemental Se and Cu2Se phase started appearing from 1200 s of deposition. The composition is changed significantly after 1500 S. Se concentration increased from 57 to 68% with the increase in the deposition time. The Cu2Se phase is dominant in the films deposited for a duration of 2000 s and the grain size increased from 1.12 to 2.15 mu m in this film. Raman analysis confirmed the presence of Se and Cu2Se phase in C1200. In C1500 and C2000 the spectra showed prominent mode corresponding to Cu2Se. The thickness of the film increased from 0.85 to 2.3 mu m with the increase in the deposition time. All the films showed p-type conductivity and resistivity reduced with increased thickness. (C) 2015 Elsevier Ltd. All rights reserved.

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This paper reports an improvement in Pt/n-GaN metal-semiconductor (MS) Schottky diode characteristics by the introduction of a layer of HfO2 (5 nm) between the metal and semiconductor interface. The resulting Pt/HfO2/n-GaN metal-insulator-semiconductor (MIS) Schottky diode showed an increase in rectification ratio from 35.9 to 98.9(@ 2V), increase in barrier height (0.52 eV to 0.63eV) and a reduction in ideality factor (2.1 to 1.3) as compared to the MS Schottky. Epitaxial n-type GaN films of thickness 300nm were grown using plasma assisted molecular beam epitaxy (PAMBE). The crystalline and optical qualities of the films were confirmed using high resolution X-ray diffraction and photoluminescence measurements. Metal-semiconductor (Pt/n-GaN) and metal-insulator-semiconductor (Pt/HfO2/n-GaN) Schottky diodes were fabricated. To gain further understanding of the Pt/HfO2/GaN interface, I-V characterisation was carried out on the MIS Schottky diode over a temperature range of 150 K to 370 K. The barrier height was found to increase (0.3 eV to 0.79 eV) and the ideality factor decreased (3.6 to 1.2) with increase in temperature from 150 K to 370 K. This temperature dependence was attributed to the inhomogeneous nature of the contact and the explanation was validated by fitting the experimental data into a Gaussian distribution of barrier heights. (C) 2015 Author(s).

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Amorphous Silicon Germanium (a-SiGe) thin films of 500 nm thickness are deposited on silicon substrates using Plasma Enhanced Chemical Vapour Deposition (PECVD). To obtain polycrystalline nature of films, thermal annealing is done at various temperature (450-600 degrees C) and time (1-10 h). The surface morphology of the pre- and post-annealed films is investigated using scanning electron microscopy (SEM) and atomic force microscopy (AFM). The crystallographic structure of the film is obtained by X-ray diffraction method. Raman spectroscopy is carried out to quantify the Ge concentration and the degree of strain relaxation in the film. Nano-indentation is performed to obtain the mechanical properties of the film. It is found that annealing reduces the surface roughness of the film and increases the Ge concentration in the film. The grain size of the film increases with increase in annealing temperature. The grain size is found to decrease with increase in annealing time up to 5 h and then increased. The results show that 550 degrees C for 5 h is the critical annealing condition for variation of structural and mechanical properties of the film. Recrystallization starts at this condition and results in finer grains. An increase in hardness value of 7-8 GPa has been observed. Grain growth occurs above this critical annealing condition and degrades the mechanical properties of the film. The strain in the film is only relaxed to about 55% even for 10 h of annealing at 600 degrees C. Transmission Electron Microscopy (TEM) observations show that the strain relaxation occurs by forming misfit dislocations and these dislocations are confined to the SiGe/Si interface. (C) 2015 Elsevier Ltd. All rights reserved.

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In spite of intense research on ZnO over the past decade, the detailed investigation about the crystallographic texture of as obtained ZnO thin films/coatings, and its deviation with growth surface is scarce. We report a systematic study about the orientation distribution of nanostructured ZnO thin films fabricated by microwave irradiation with the variation of substrates and surfactants. The nanostructured films comprising of ZnO nanorods are grown on semiconductor substrates such as Si(100), Ge(100)], conducting substrates (ITO-coated glass, Cr coated Si), and polymer coated Si (PMMA/Si) to examine the respective development of crystallographic texture. The ZnO deposited on semiconductor substrates yieldsmixed texture, whereas c-axis oriented ZnO nanostructured films are obtained by conducting substrate, and PMMA coated Si substrates. Among all the surfactants, nanostructured film produced by using the lower molecular weight of polymeric surfactants (polyvinylpyrrolidone) shows a stronger (0002) texture, and that can be tuned to (10 - 10) by increasing the molecular weight of the surfactant. The strongest basal pole is achieved for the ZnO deposited on PMMA coated Si as substrate, and cetyl-trimethyl ammonium bromide as cationic surfactant. The texture analysis is carried out by X-ray pole figure analysis using the Schultz reflection method. (C) 2015 Elsevier B.V. All rights reserved.

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Buffer leakage is an important parasitic loss mechanism in AlGaN/GaN high electron mobility transistors (HEMTs) and hence various methods are employed to grow semi-insulating buffer layers. Quantification of carrier concentration in such buffers using conventional capacitance based profiling techniques is challenging due to their fully depleted nature even at zero bias voltages. We provide a simple and effective model to extract carrier concentrations in fully depleted GaN films using capacitance-voltage (C-V) measurements. Extensive mercury probe C-V profiling has been performed on GaN films of differing thicknesses and doping levels in order to validate this model. Carrier concentrations as extracted from both the conventional C-V technique for partially depleted films having the same doping concentration, and Hall measurements show excellent agreement with those predicted by the proposed model thus establishing the utility of this technique. This model can be readily extended to estimate background carrier concentrations from the depletion region capacitances of HEMT structures and fully depleted films of any class of semiconductor materials.

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Nonpolar a-GaN (11-20) epilayers were grown on r-plane (1-102) sapphire substrates using plasma assisted molecular beam epitaxy. High resolution x-ray diffractometer confirmed the orientation of the grown film. Effect of the Ga/N ratio on the morphology and strain of a-GaN epilayers was compared and the best condition was obtained for the nitrogen flow of 1 sccm. Atomic force microscopy was used to analyze the surface morphology while the strain in the film was quantitatively measured using Raman spectroscopy and qualitatively analyzed by reciprocal space mapping technique. UV photo response of a-GaN film was measured after fabricating a metal-semiconductor-metal structure over the film with gold metal. The external quantum efficiency of the photodetectors fabricated in the (0002) polar and (11-20) nonpolar growth directions were compared in terms of responsivity and nonpolar GaN showed the best sensitivity at the cost of comparatively slow response time. (C) 2015 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.

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We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (V-FB), oxide trapped charge (Q(ot)), dielectric constant (kappa) and equivalent oxide thicknesses are calculated from capacitance-voltage (C-V) curves. The C-V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 A degrees C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-kappa insulating layer, which might be useful in Si and polymer based flexible devices.

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Films of Ti-Si-N obtained by reactively sputtering a TiSi_2, a Ti_5Si_3, or a Ti_3Si target are either amorphous or nanocrystalline in structure. The atomic density of some films exceeds 10^23 at./cm^3. The room-temperature resistivity of the films increases with the Si and the N content. A thermal treatment in vacuum at 700 °C for 1 hour decreases the resistivity of the Ti-rich films deposited from the Ti_5Si_3 or the Ti_3Si target, but increases that of the Si-rich films deposited from the TiSi_2 target when the nitrogen content exceeds about 30 at. %.

Ti_(34)Si_(23)N_(43) deposited from the Ti_5Si_3 target is an excellent diffusion barrier between Si and Cu. This film is a mixture of nanocrystalline TiN and amorphous SiN_x. Resistivity measurement from 80 K to 1073 K reveals that this film is electrically semiconductor-like as-deposited, and that it becomes metal-like after an hour annealing at 1000 °C in vacuum. A film of about 100 nm thick, with a resistivity of 660 µΩcm, maintains the stability of Si n+p shallow junction diodes with a 400 nm Cu overlayer up to 850 °C upon 30 min vacuum annealing. When used between Si and Al, the maximum temperature of stability is 550 °C for 30 min. This film can be etched in a CF_4/O_2 plasma.

The amorphous ternary metallic alloy Zr_(60)Al_(15)Ni_(25) was oxidized in dry oxygen in the temperature range 310 °C to 410 °C. Rutherford backscattering and cross-sectional transmission electron microscopy studies suggest that during this treatment an amorphous layer of zirconium-aluminum-oxide is formed at the surface. Nickel is depleted from the oxide and enriched in the amorphous alloy below the oxide/alloy interface. The oxide layer thickness grows parabolically with the annealing duration, with a transport constant of 2.8x10^(-5) m^2/s x exp(-1.7 eV/kT). The oxidation rate is most likely controlled by the Ni diffusion in the amorphous alloy.

At later stages of the oxidation process, precipitates of nanocrystalline ZrO_2 appear in the oxide near the interface. Finally, two intermetallic phases nucleate and grow simultaneously in the alloy, one at the interface and one within the alloy.

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Photovoltaic energy conversion represents a economically viable technology for realizing collection of the largest energy resource known to the Earth -- the sun. Energy conversion efficiency is the most leveraging factor in the price of energy derived from this process. This thesis focuses on two routes for high efficiency, low cost devices: first, to use Group IV semiconductor alloy wire array bottom cells and epitaxially grown Group III-V compound semiconductor alloy top cells in a tandem configuration, and second, GaP growth on planar Si for heterojunction and tandem cell applications.

Metal catalyzed vapor-liquid-solid grown microwire arrays are an intriguing alternative for wafer-free Si and SiGe materials which can be removed as flexible membranes. Selected area Cu-catalyzed vapor-liquid solid growth of SiGe microwires is achieved using chlorosilane and chlorogermane precursors. The composition can be tuned up to 12% Ge with a simultaneous decrease in the growth rate from 7 to 1 μm/min-1. Significant changes to the morphology were observed, including tapering and faceting on the sidewalls and along the lengths of the wires. Characterization of axial and radial cross sections with transmission electron microscopy revealed no evidence of defects at facet corners and edges, and the tapering is shown to be due to in-situ removal of catalyst material during growth. X-ray diffraction and transmission electron microscopy reveal a Ge-rich crystal at the tip of the wires, strongly suggesting that the Ge incorporation is limited by the crystallization rate.

Tandem Ga1-xInxP/Si microwire array solar cells are a route towards a high efficiency, low cost, flexible, wafer-free solar technology. Realizing tandem Group III-V compound semiconductor/Si wire array devices requires optimization of materials growth and device performance. GaP and Ga1-xInxP layers were grown heteroepitaxially with metalorganic chemical vapor deposition on Si microwire array substrates. The layer morphology and crystalline quality have been studied with scanning electron microscopy and transmission electron microscopy, and they provide a baseline for the growth and characterization of a full device stack. Ultimately, the complexity of the substrates and the prevalence of defects resulted in material without detectable photoluminescence, unsuitable for optoelectronic applications.

Coupled full-field optical and device physics simulations of a Ga0.51In0.49P/Si wire array tandem are used to predict device performance. A 500 nm thick, highly doped "buffer" layer between the bottom cell and tunnel junction is assumed to harbor a high density of lattice mismatch and heteroepitaxial defects. Under simulated AM1.5G illumination, the device structure explored in this work has a simulated efficiency of 23.84% with realistic top cell SRH lifetimes and surface recombination velocities. The relative insensitivity to surface recombination is likely due to optical generation further away from the free surfaces and interfaces of the device structure.

Finally, GaP has been grown free of antiphase domains on Si (112) oriented substrates using metalorganic chemical vapor deposition. Low temperature pulsed nucleation is followed by high temperature continuous growth, yielding smooth, specular thin films. Atomic force microscopy topography mapping showed very smooth surfaces (4-6 Å RMS roughness) with small depressions in the surface. Thin films (~ 50 nm) were pseudomorphic, as confirmed by high resolution x-ray diffraction reciprocal space mapping, and 200 nm thick films showed full relaxation. Transmission electron microscopy showed no evidence of antiphase domain formation, but there is a population of microtwin and stacking fault defects.

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Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.