Paving the way to nanoionics: atomic origin of barriers for ionic transport through interfaces

The blocking of ion transport at interfaces strongly limits the performance of electrochemical nanodevices for energy applications. The barrier is believed to arise from space-charge regions generated by mobile ions by analogy to semiconductor junctions. Here we show that something different is at play by studying ion transport in a bicrystal of yttria (9% mol) stabilized zirconia (YSZ), an emblematic oxide ion conductor. Aberration-corrected scanning transmission electron microscopy (STEM) provides structure and composition at atomic resolution, with the sensitivity to directly reveal the oxygen ion profile. We find that Y segregates to the grain boundary at Zr sites, together with a depletion of oxygen that is confined to a small length scale of around 0.5 nm. Contrary to the main thesis of the space-charge model, there exists no evidence of a long-range O vacancy depletion layer. Combining ion transport measurements across a single grain boundary by nanoscale electrochemical strain microscopy (ESM), broadband dielectric spectroscopy measurements, and density functional calculations, we show that grain-boundary-induced electronic states act as acceptors, resulting in a negatively charged core. Ultimately, it is this negative charge which gives rise to the barrier for ion transport at the grain boundary

Low-voltage driven ZnS:Mn MIS and MISIM thin film electroluminescent devices with Eu2O3 insulator layer

AC thin film electroluminescent devices of MIS and MISIM have been fabricated with a novel dielectric layer of Eu2O3 as an insulator. The threshold voltage for light emission is found to depend strongly on the frequency of excitation source in these devices. These devices are fabricated with an active layer of ZnS:Mn and a novel dielectric layer of Eu2O3 as an insulator. The observed frequency dependence of brightness-voltage characteristics has been explained on the basis of the loss characteristic of the insulator layer. Changes in the threshold voltage and brightness with variation in emitting or insulating film thickness have been investigated in metal-insulator-semiconductor (MIS) structures. It has been found that the decrease in brightness occurring with decreasing ZnS layer thickness can be compensated by an increase in brightness obtained by reducing the insulator thickness. The optimal condition for low threshold voltage and higher stability has been shown to occur when the active layer to insulator thickness ratio lies between one and two.

Molecular Beam Epitaxial Growth of III-V Semiconductor Nanostructures on Silicon Substrates

The main focus and concerns of this PhD thesis is the growth of III-V semiconductor nanostructures (Quantum dots (QDs) and quantum dashes) on silicon substrates using molecular beam epitaxy (MBE) technique. The investigation of influence of the major growth parameters on their basic properties (density, geometry, composition, size etc.) and the systematic characterization of their structural and optical properties are the core of the research work. The monolithic integration of III-V optoelectronic devices with silicon electronic circuits could bring enormous prospect for the existing semiconductor technology. Our challenging approach is to combine the superior passive optical properties of silicon with the superior optical emission properties of III-V material by reducing the amount of III-V materials to the very limit of the active region. Different heteroepitaxial integration approaches have been investigated to overcome the materials issues between III-V and Si. However, this include the self-assembled growth of InAs and InGaAs QDs in silicon and GaAx matrices directly on flat silicon substrate, sitecontrolled growth of (GaAs/In0,15Ga0,85As/GaAs) QDs on pre-patterned Si substrate and the direct growth of GaP on Si using migration enhanced epitaxy (MEE) and MBE growth modes. An efficient ex-situ-buffered HF (BHF) and in-situ surface cleaning sequence based on atomic hydrogen (AH) cleaning at 500 °C combined with thermal oxide desorption within a temperature range of 700-900 °C has been established. The removal of oxide desorption was confirmed by semicircular streaky reflection high energy electron diffraction (RHEED) patterns indicating a 2D smooth surface construction prior to the MBE growth. The evolution of size, density and shape of the QDs are ex-situ characterized by atomic-force microscopy (AFM) and transmission electron microscopy (TEM). The InAs QDs density is strongly increased from 108 to 1011 cm-2 at V/III ratios in the range of 15-35 (beam equivalent pressure values). InAs QD formations are not observed at temperatures of 500 °C and above. Growth experiments on (111) substrates show orientation dependent QD formation behaviour. A significant shape and size transition with elongated InAs quantum dots and dashes has been observed on (111) orientation and at higher Indium-growth rate of 0.3 ML/s. The 2D strain mapping derived from high-resolution TEM of InAs QDs embedded in silicon matrix confirmed semi-coherent and fully relaxed QDs embedded in defectfree silicon matrix. The strain relaxation is released by dislocation loops exclusively localized along the InAs/Si interfaces and partial dislocations with stacking faults inside the InAs clusters. The site controlled growth of GaAs/In0,15Ga0,85As/GaAs nanostructures has been demonstrated for the first time with 1 μm spacing and very low nominal deposition thicknesses, directly on pre-patterned Si without the use of SiO2 mask. Thin planar GaP layer was successfully grown through migration enhanced epitaxy (MEE) to initiate a planar GaP wetting layer at the polar/non-polar interface, which work as a virtual GaP substrate, for the GaP-MBE subsequently growth on the GaP-MEE layer with total thickness of 50 nm. The best root mean square (RMS) roughness value was as good as 1.3 nm. However, these results are highly encouraging for the realization of III-V optical devices on silicon for potential applications.

THEORY OF ELECTRICAL CHARACTERISTICS OF A SCHOTTKY-BARRIER HAVING EXPONENTIALLY DISTRIBUTED IMPURITY STATES AND METAL-INSULATOR METAL STRUCTURES

The metal-insulator or metal-amorphous semiconductor blocking contact is still not well understood. Here, we discuss the steady state characteristics of a non-intimate metal-insulator Schottky barrier. We consider an exponential distribution (in energy) of impurity states in addition to impurity states at a single energy level within the depletion region. We present analytical expressions for the electrical potential, field, thickness of depletion region, capacitance, and charge accumulated in the depletion region. We also discuss ln I versus V(ap) data. Finally, we compare the characteristics in three cases: (i) impurity states at only a single energy level; (ii) uniform energy distribution of impurity states; and (iii) exponential energy distribution of impurity states.In general, the electrical characteristics of Schottky barriers and metal-insulator-metal structures with Schottky barriers depend strongly on the energy distribution of impurity states.

THEORY OF NON-STEADY-STATE ELECTRICAL CHARACTERISTICS OF METAL-INSULATOR-METAL STRUCTURES WITH SCHOTTKY BARRIERS AND UNIFORMLY DISTRIBUTED INTERFACE IMPURITY STATES

The metal-insulator (or amorphous semiconductor) blocking contact is still not well understood. In the present paper, we discuss the non steady state characteristics of Metal-lnsulator-Metal Structure with non-intimate blocking contacts (i.e. Metal-Oxide-Insulator-Metal Structure). We consider a uniform distribution (in energy) of impurity states in addition to impurity states at a single energy level within the depletion region. We discuss thermal as well as isothermal characteristics and present expressions for the temperature of maximum current (T-m) and a method to calculate the density of uniformly distributed impurity states. The variation of mobility with electrical field has also been considered. Finally we plot the theoretical curves under different conditions. The present results are closing into available experimental results.

Theory of electrical characteristics for metal-oxide-insulator Schottky barrier and metal-insulator-metal structures

The metal-insulator or metal-amorphous semiconductor blocking contact is still not well understood. Here, the intimate metal-insulator and metal-oxide-insulator contact are discussed. Further, the steady-state characteristics of metal-oxide-insulator-metal structures are also discussed. Oxide is an insulator with wider energy band gap (about 50 Å thick). A uniform energetic distribution of impurities is considered in addition to impurities at a single energy level inside the surface charge region at the oxide-insulator interface. Analytical expressions are presented for electrical potential, field, thickness of the depletion region, capacitance, and charge accumulated in the surface charge region. The electrical characteristics are compared with reference to relative densities of two types of impurities. ln I is proportional to the square root of applied potential if energetically distributed impurities are relatively important. However, distribution of the electrical potential is quite complicated. In general energetically distributed impurities can considerably change the electrical characteristics of these structures.

Insulator-to-metal transition driven by clustering of solitons in polyacetylene

It's believed that the simple Su-Schrieffer-Heeger Hamiltonian can not predict the insulator to metal transition of transpolyacetylene (t-PA). The soliton lattice configuration at a doping level y=6% still has a semiconductor gap. Disordered distributions of solitons close the gap, but the electronic states around the Fermi energy are localized. However, within the same framework, it is possible to show that a cluster of solitons can produce dramatic changes in the electronic structure, allowing an insulator-to-metal transition.

Photocatalytic activity of semiconductor sulfide heterostructures

This paper reports a theoretical and experimental study of the heterostructure photocatalytic activity in a CdS or ZnS and CdS@ZnS decorated system prepared by a microwave assisted solvothermal (MAS) method. A theoretical model of the decorated system was created in order to analyze the electronic transition mainly in their interface. The results show that CdS and ZnS interfaces produce an electron charge transfer from the CdS electron-populated clusters to the ZnS hole-populated clusters which helps to enhance the photocatalytic activity of the CdS@ZnS decorated system. © 2013 The Royal Society of Chemistry.

Filmes nanoestruturados aplicados ao sistema de língua eletrônica: um estudo de interfaces

Pós-graduação em Ciência e Tecnologia de Materiais - FC

Hopping-tunneling model to describe electric charge injection at metal/organic semiconductor heterojunctions

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Advanced SPM studies on the growth of ultrathin films of organic semiconductors at metal and dielectric interfaces

Many studies on the morphology, molecular orientation, device performance, substrate nature and growth parameter dependence have been carried out since the proposal of Sexithiophene (6T) for organic electronics [ ] However, these studies were mostly performed on films thicker than 20nm and without specifically addressing the relationship between morphology and molecular orientation within the nano and micro structures of ultrathin films of 0-3 monolayers. In 2004, the observation that in OFETs only the first few monolayers at the interface in contact with the gate insulator contribute to the charge transport [ ], underlined the importance to study submonolayer films and their evolution up to a few monolayers of thickness with appropriate experimental techniques. We present here a detailed Non-contact Atomic Force Microscopy and Scanning Tunneling Microscopy study on various substrates aiming at the investigation of growth mechanisms. Most reported similar studies are performed on ideal metals in UHV. However it is important to investigate the details of organic film growth on less ideal and even technological surfaces and device testpatterns. The present work addresses the growth of ultra thin organic films in-situ and quasi real-time by NC-AFM. An organic effusion cell is installed to evaporate the organic material directly onto the SPM sample scanning stage.

Impedance analysis of Al2O3/H-terminated diamond metal-oxide-semiconductor structures

Impedance spectroscopy (IS) analysis is carried out to investigate the electrical properties of the metal-oxide-semiconductor (MOS) structure fabricated on hydrogen-terminated single crystal diamond. The low-temperature atomic layer deposition Al2O3 is employed as the insulator in the MOS structure. By numerically analysing the impedance of the MOS structure at various biases, the equivalent circuit of the diamond MOS structure is derived, which is composed of two parallel capacitive and resistance pairs, in series connection with both resistance and inductance. The two capacitive components are resulted from the insulator, the hydrogenated-diamond surface, and their interface. The physical parameters such as the insulator capacitance are obtained, circumventing the series resistance and inductance effect. By comparing the IS and capacitance-voltage measurements, the frequency dispersion of the capacitance-voltage characteristic is discussed.

Optical properties of semiconductor quantum wires

This thesis presents theoretical investigations of the sub band structure and optical properties of semiconductor quantum wires. For the subband structure, we employ multiband effective-mass theory and the effective bond-orbital model both of which fully account for the band mixing and material anisotropy. We also treat the structure geometry in detail taking account of such effects as the compositional grading across material interfaces. Based on the subband structure, we calculate optical properties of quantum-wire structures. A recuring theme is the cross-over from one- to ~wo-dimensional behavior in these structures. This complicated behavior procludes the application of simple theoretical models to obtain the electronic structure. In particular, we calculate laser properties of quantum wires grown in V-grooves and find enhanced performance compared with quantum-well lasers. We also investigate optical anisotropy in quantum-wire arrays and propose an electro-optic device based on such structures.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.